Design and performance evaluation of chip capacitors on microprocessor packaging

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819220

T. Yew, Yuan-liang Li, C. Chung, D. Figueroa

引用次数: 6

Abstract

This paper describes the different chip capacitor placement design on Intel's latest Celeron CPU package. The evaluation of its effectiveness in the power delivery network and final impact on CPU performance are also discussed.

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微处理器封装上芯片电容器的设计和性能评估

本文介绍了英特尔最新的赛扬CPU封装上不同的芯片电容布局设计。并讨论了其在电力输送网络中的有效性评估以及对CPU性能的最终影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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