IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)最新文献

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Efficient and accurate extraction of frequency-dependent resistance and inductance parameters of interconnects 高效准确地提取与频率相关的互连电阻和电感参数
Wen Wang, J. Fang, Yuzhe Chen
{"title":"Efficient and accurate extraction of frequency-dependent resistance and inductance parameters of interconnects","authors":"Wen Wang, J. Fang, Yuzhe Chen","doi":"10.1109/EPEP.1999.819239","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819239","url":null,"abstract":"This paper presents a new scheme for generating numerical meshes for computing the frequency-dependent resistance and inductance of transmission lines with rectangular cross-sections. The proposed mesh conforms to frequency-dependent spatial distribution of current. The method ensures accurate numerical solutions with relatively small numbers of mesh elements. The numerical results and the efficiency of our method are compared with those of FastHenry.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116903910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Physical layer design of a 1.6 GB/s DRAM bus 物理层设计了1.6 GB/s的DRAM总线
A. Moncayo, S. Hindi, Ching-Chao Huang, R. Kollipara, H. Liaw, D. Nguyen, D. Perino, A. Sarfaraz, C. Yuan, M. Leddige, J. McCall, X. Moua, J. Salmon
{"title":"Physical layer design of a 1.6 GB/s DRAM bus","authors":"A. Moncayo, S. Hindi, Ching-Chao Huang, R. Kollipara, H. Liaw, D. Nguyen, D. Perino, A. Sarfaraz, C. Yuan, M. Leddige, J. McCall, X. Moua, J. Salmon","doi":"10.1109/EPEP.1999.819183","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819183","url":null,"abstract":"This paper describes an innovative design and modeling methodology for development of a high performance memory bus with data signaling bandwidth of up to 1.6 gigabytes per second. Data signals operate at 800 megabits per second transfer rate. The clock frequency is 400 MHz and the signal edge transition time is 200 ps. Due to the extremely high frequencies involved, overall system electrical performance must be optimized. By following the methodology outlined in this paper, good correlation was obtained between simulated and measured results.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125189304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design rule development for microwave flip chip applications 微波倒装芯片应用的设计规则开发
D. Staiculescu, J. Laskar, J. Mather
{"title":"Design rule development for microwave flip chip applications","authors":"D. Staiculescu, J. Laskar, J. Mather","doi":"10.1109/EPEP.1999.819232","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819232","url":null,"abstract":"This paper presents a novel approach for analysis of factors to be considered when designing a flip chip package. It includes the design of an experiment and statistical analysis of the outputs. The most significant factors are found to be, from most to least important, the length of the area where the device and the substrate overlap (referred to as conductor overlap), the bump diameter and the width of the coplanar waveguide transmission line launch. These results are valid for conductor overlaps between 300 and 500 /spl mu/m. For a lower overlap value (120 /spl mu/m), the bump height also becomes significant. The substrate thickness in the 10 to 25 mil interval is found to be statistically insignificant, and therefore can be eliminated from further analysis.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125198994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Electronic packaging for microwave multichip modules 微波多芯片模块的电子封装
A. Piloto
{"title":"Electronic packaging for microwave multichip modules","authors":"A. Piloto","doi":"10.1109/EPEP.1999.819181","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819181","url":null,"abstract":"Summary form only given. Modern radio frequency (RF) systems including radar/electronically scanned arrays are electronic systems in which MCMs are beginning to be applied. Conventional radars/RF systems generally have been operated at frequencies of about 220 MHz to 94 GHz, a spread of over eight octaves. The development of monolithic microwave integrated circuit (MMIC) and application specific integrated circuit (ASIC) semiconductor technology has given rise to wider spread usage of analog and mixed mode (analog and digital) MCM designs within the major segments of the RF system. The challenge to MCM design is the incorporation of passive and active RF and DC components within a single MCM and the relationship between the materials, mechanical design and electrical performance of the MCM. As microwave semiconductor technology continues to evolve, so shall the demand on all aspects of analog and mixed mode MCMs.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117100905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transmission link radiation: localized defect contribution 传输链路辐射:局部缺陷贡献
E. Martinod, P. Nadeau, N. Feix, M. Lalande-Guionie, A. Reineix, B. Jecko
{"title":"Transmission link radiation: localized defect contribution","authors":"E. Martinod, P. Nadeau, N. Feix, M. Lalande-Guionie, A. Reineix, B. Jecko","doi":"10.1109/EPEP.1999.819211","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819211","url":null,"abstract":"Theoretical and experimental transient methods are proposed for radiation evaluation of localized defects on transmission links (such as a slot on a coaxial cable shield). Thereafter, a complete electrical link between equipment boxes is analyzed. This paper describes how the asymmetry of the transmission line created by different terminations has a direct impact on the level of the radiation.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125828216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Toward a novel planar circuit compatible silicon micromachined waveguide 一种新型兼容平面电路的硅微机械波导
James Becker, Linda P. B. Katehi
{"title":"Toward a novel planar circuit compatible silicon micromachined waveguide","authors":"James Becker, Linda P. B. Katehi","doi":"10.1109/EPEP.1999.819230","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819230","url":null,"abstract":"A novel, completely packaged planar-fed silicon micromachined waveguide/resonator is proposed. Simulated results for a Ka-band resonator are given, along with initial results of the required three-dimensional photolithographic patterning along sloping sidewalls.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"466 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124373427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Noise verification across 3 levels of packaging hierarchy for the IBM G5/G6 mainframes 对IBM G5/G6大型机进行跨3个包装层次的噪声验证
H. Smith, S. Kuppinger, P. Venkatachalam, W. Becker
{"title":"Noise verification across 3 levels of packaging hierarchy for the IBM G5/G6 mainframes","authors":"H. Smith, S. Kuppinger, P. Venkatachalam, W. Becker","doi":"10.1109/EPEP.1999.819185","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819185","url":null,"abstract":"For IBM's G5/G6 mainframes, both signal rise times and machine cycle times have reduced to the point where signal integrity issues such as noise containment at the system level represent a significant challenge for comprehensive verification of the off-chip nets. The total noise is composed of coupling noise and the switching or delta-i noise. These noise sources are evaluated for all MCM and board nets to ensure coverage is not compromised. The noise verification process has been developed within IBM's S/390 division over several generations of technology and machine designs (Rude, 1994; Venkatachalam et al, 1993; Smith and Katopis, 1996). It is intended to provide a bounding calculation of total noise and identify nets which exceed their design limits for subsequent rerouting. Bounding calculation accuracy is a function of the resolution of deterministic parameters such as physical layouts and statistical variations such as switching time uncertainty. There are several packaging components which must be characterized before system level noise analysis can be performed on the interconnects. The packaging components are the MCM, its board, the memory cards, and the complex connector structures used at the package interfaces. The glass-ceramic MCM contains 20 plane pairs of wiring in ceramic and one plane pair of wiring in thin film. The board has six plane pairs of wiring. The memory cards have five plane pairs of wiring. This paper addresses noise checking across the three levels of packaging which include the on-MCM nets as well as signals from chips on the MCM to chips on the memory card through the board.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133068370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Modeling the effects of non-linear materials in de-coupling components of digital systems 模拟非线性材料对数字系统解耦组件的影响
G. Cokkinides, B. Beker
{"title":"Modeling the effects of non-linear materials in de-coupling components of digital systems","authors":"G. Cokkinides, B. Beker","doi":"10.1109/EPEP.1999.819202","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819202","url":null,"abstract":"This paper describes a physics-based numerical approach to building circuit models for electronic components that are made using nonlinear dielectrics. The resulting models are intended for use in time-domain circuit simulators to assess the effects of material nonlinearity on the electrical performance of such components as discrete, on-substrate and on-chip de-coupling capacitors. A 3D electrostatic field solver is modified to take into account the nonlinear field dependence of the dielectric material and is employed to calculate the Q-V curve for any capacitive structure. Subsequently, a time integration method (similar to that used in SPICE) is utilized to devise an appropriate time-stepping algorithm for the current-charge relationship of a nonlinear capacitor that can be used to simulate the time-domain electrical characteristics of such passive components. Sample results are also provided to illustrate the methodology.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133756751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Half-conductive coupling for chip-to-chip connections 用于芯片到芯片连接的半导电耦合
W. Pan, C. De Tandt, F. Devisch, R. Vounckx, M. Kuijk
{"title":"Half-conductive coupling for chip-to-chip connections","authors":"W. Pan, C. De Tandt, F. Devisch, R. Vounckx, M. Kuijk","doi":"10.1109/EPEP.1999.819187","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819187","url":null,"abstract":"A half-conductive layer forms a resistive network and is proposed to offer electrical interconnects between two mating substrates. Experimental results prove that sufficient conduction can be obtained for signal transmission at a reasonable crosstalk level.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123563255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fast simulation method for single and coupled lossy lines with frequency-dependent parameters based on triangle impulse responses 一种基于三角形脉冲响应的含频率参数的单线和耦合有损线的快速仿真方法
Zhaoqing Chen, W. Becker, G. Katopis
{"title":"A fast simulation method for single and coupled lossy lines with frequency-dependent parameters based on triangle impulse responses","authors":"Zhaoqing Chen, W. Becker, G. Katopis","doi":"10.1109/EPEP.1999.819238","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819238","url":null,"abstract":"This paper describes a fast simulation method for single and coupled lossy transmission lines based on triangle impulse responses. The method can be applied to simulating systems consisting of large numbers of lossy transmission lines with frequency-dependent parameters in high-speed IC package design.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126080846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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