IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)最新文献_第5页

Challenges in the packaging of an eight way server 封装八路服务器的挑战

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819182

T. Aldridge

{"title":"Challenges in the packaging of an eight way server","authors":"T. Aldridge","doi":"10.1109/EPEP.1999.819182","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819182","url":null,"abstract":"Summary form only given. The Saber system by Intel's Enterprise Server Division is an excellent example of the multivariable driven nature of system packaging for cost, performance, use and service that characterizes high volume servers. The Saber is based around the Intel Xeon processor and the Profusion eight way capable chip-set and provides excellent performance on TPM-C performance and cost/performance benchmarks. The system supports eight Pentium III Xeon processors with up to 32 GB of PC-100 SDRAM, 10 hot plug PCI-66 slots and fully redundant power and cooling. The package is compliant to major OEM requirements, being 7U in height and 28\" deep with space for hot plug hard drives to support the OS boot and swap space requirements as well as some data space. This presentation describes some of the challenges and solutions to the packaging of the Saber eight way system. The system required chip-set and board-set partitioning that supported the dual 100 MHz front side buses accommodating the Pentium III Xeon processors and the memory array. Use of high performance connectors and improved board materials were made while simulation and verification allowed the integration to meet cost and performance goals. For package longevity, processor power was set at 75 W in anticipation of one more performance stepping, putting a serious load on cooling. Airflow paths for the processors, memory and PCI slots were integrated into a complete model along with the chassis and power supplies to arrive at a solution. User serviceability and OEM differentiability were key to industrial design and packaging of the system and its modules.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of cross-over lines on delay time of two parallel global wires [IC interconnects] 交叉线对两根并联全局线延迟时间的影响[IC互连]

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819192

Sangwoo Kim, C. S. Chang, D. Neikirk

引用次数: 0

Simultaneous switching, noise, and reliability analyses of VLSI core logic VLSI核心逻辑的同步开关、噪声和可靠性分析

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819213

I. Hajj

{"title":"Simultaneous switching, noise, and reliability analyses of VLSI core logic","authors":"I. Hajj","doi":"10.1109/EPEP.1999.819213","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819213","url":null,"abstract":"Summary form only given. The rapid advances in process technology have brought many new challenges to IC design. Interconnects are becoming one of the most significant factors in determining the performance of the design. With increased design complexity and reduced feature size, interconnects become more resistive, have more coupling, and cover longer distances on the chip. With the increase in operating frequencies, inductive effects also influence chip performance. Therefore, in order to produce high performance and reliable designs, the interactions in the operation of the devices in terms of the design and the interconnects, including signal lines, power distribution and clock networks, should be correctly modeled and clearly understood early in the design cycle. In this paper, we focus on voltage drop or voltage variations in power and ground buses and delay and crosstalk noise in signal interconnects. We show by theory and by examples that some of the recently published results and some of the techniques followed in industry for dealing with these problems could produce misleading (or erroneous) results. We first show the relationship between switching and timing to reliability and noise analysis, and derive fast input independent techniques to produce tight bounds on worst-case voltage variations and worst-case current flows in the power bus and on crosstalk noise and delay variations in the signal lines. The techniques we develop are also applicable to the estimation of substrate noise and to maximum leakage currents.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114232755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel time domain algorithm for field excited lossy transmission lines 场激励损耗传输线的时域算法

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819228

P. Nordholz, F. Ktata

引用次数: 3

On-chip wiring design challenges for GHz operation 千兆赫操作的片上布线设计挑战

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819190

A. Deutsch, H. Smith, G. Kopcsay, D. Edelstein, P. Coteus

引用次数: 13

Reliability and performance tradeoffs in the design of on-chip power delivery and interconnects 片上供电和互连设计中的可靠性和性能权衡

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819191

G. Taylor, T. Arabi, H. Greub, R. Muyshondt, A. Manthe, P. Aminzadeh

{"title":"Reliability and performance tradeoffs in the design of on-chip power delivery and interconnects","authors":"G. Taylor, T. Arabi, H. Greub, R. Muyshondt, A. Manthe, P. Aminzadeh","doi":"10.1109/EPEP.1999.819191","DOIUrl":"https://doi.org/10.1109/EPEP.1999.819191","url":null,"abstract":"The performance of CMOS integrated circuits has always been, and continues to be, limited by reliability considerations. Performance, reliability, and cost are traded off through voltage and temperature specifications. Higher operating voltage raises performance but impacts reliability both directly and through increased temperatures unless extra cooling is supplied. Lower temperatures yield higher performance and higher reliability but also higher cost. As silicon technology scales, these trade-offs are becoming more pronounced. While hot carrier injection may be becoming less significant as semiconductor technology scales to thinner gate oxides, other mechanisms are becoming more significant. The temperature acceleration of oxide breakdown is increasing with decreasing thickness (Degraeve et al., 1999), current densities are increasing, further stressing electromigration, and inductive noise effects are becoming more significant, while soft error susceptibility is increasing (Dai et al., 1999). There are many mechanisms that can lead to the failure of an integrated circuit. Hot carrier injection has been a significant issue, but has been surpassed by other mechanisms as CMOS technology has advanced into the deep submicron regime. In this paper, we focus mainly on the design and validations issues associated with oxide wear-out failure mechanisms.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130781667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Laguerre-SVD reduced order modeling Laguerre-SVD降阶建模

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819236

L. Knockaert, D. Zutter

引用次数: 4

Off-chip delta-I noise modeling and measurement methodology 片外δ - 1噪声建模和测量方法

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819219

N. Pham, M. Cases, J. Nissen

引用次数: 1

Characteristic impedance of microstrip on silicon 硅基微带的特性阻抗

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819221

D.F. Williams, B. Alpert

引用次数: 9

Operating frequency trends for high performance off-chip buses 高性能片外总线的工作频率趋势

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI: 10.1109/EPEP.1999.819189

G. Katopis

引用次数: 6