Impact of cross-over lines on delay time of two parallel global wires [IC interconnects]

Abstract

The length of the address or data lines between the ALU and cache sections on a microprocessor chip may exceed 10 mm. To minimize the delay time impact due to the signal line series resistance, one may use the 2/spl times/2 /spl mu/m/sup 2/ lines on the M7 and/or M8 layers for the address and data buses. We investigate the delay time impact due to the series resistance for two coupled lines on M7, including the influence of the cross-over lines on the M6 and M8 layers. The cross-over lines on M6 and M8 cause increase in self-capacitance and reduction in mutual-capacitance for two adjacent address lines on M7. The delay time of the address or data information, in +/+ and +/- configurations, is affected differently for different line length.