交叉线对两根并联全局线延迟时间的影响[IC互连]

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819192

Sangwoo Kim, C. S. Chang, D. Neikirk

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引用次数: 0

摘要

微处理器芯片上ALU和缓存段之间的地址或数据线的长度可能超过10mm。为了尽量减少由于信号线串联电阻造成的延迟时间影响，可以在M7和/或M8层上使用2/spl times/2 /spl mu/m/sup 2/线作为地址和数据总线。我们研究了M7上的两个耦合线的串联电阻对延迟时间的影响，包括交叉线对M6和M8层的影响。M6和M8上的交叉线使M7上相邻的两条地址线的自电容增大，互电容减小。在+/+和+/-配置中，不同的线路长度对地址或数据信息的延迟时间有不同的影响。

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Impact of cross-over lines on delay time of two parallel global wires [IC interconnects]

The length of the address or data lines between the ALU and cache sections on a microprocessor chip may exceed 10 mm. To minimize the delay time impact due to the signal line series resistance, one may use the 2/spl times/2 /spl mu/m/sup 2/ lines on the M7 and/or M8 layers for the address and data buses. We investigate the delay time impact due to the series resistance for two coupled lines on M7, including the influence of the cross-over lines on the M6 and M8 layers. The cross-over lines on M6 and M8 cause increase in self-capacitance and reduction in mutual-capacitance for two adjacent address lines on M7. The delay time of the address or data information, in +/+ and +/- configurations, is affected differently for different line length.

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IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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