Noise verification across 3 levels of packaging hierarchy for the IBM G5/G6 mainframes

Abstract

For IBM's G5/G6 mainframes, both signal rise times and machine cycle times have reduced to the point where signal integrity issues such as noise containment at the system level represent a significant challenge for comprehensive verification of the off-chip nets. The total noise is composed of coupling noise and the switching or delta-i noise. These noise sources are evaluated for all MCM and board nets to ensure coverage is not compromised. The noise verification process has been developed within IBM's S/390 division over several generations of technology and machine designs (Rude, 1994; Venkatachalam et al, 1993; Smith and Katopis, 1996). It is intended to provide a bounding calculation of total noise and identify nets which exceed their design limits for subsequent rerouting. Bounding calculation accuracy is a function of the resolution of deterministic parameters such as physical layouts and statistical variations such as switching time uncertainty. There are several packaging components which must be characterized before system level noise analysis can be performed on the interconnects. The packaging components are the MCM, its board, the memory cards, and the complex connector structures used at the package interfaces. The glass-ceramic MCM contains 20 plane pairs of wiring in ceramic and one plane pair of wiring in thin film. The board has six plane pairs of wiring. The memory cards have five plane pairs of wiring. This paper addresses noise checking across the three levels of packaging which include the on-MCM nets as well as signals from chips on the MCM to chips on the memory card through the board.