物理层设计了1.6 GB/s的DRAM总线

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819183

A. Moncayo, S. Hindi, Ching-Chao Huang, R. Kollipara, H. Liaw, D. Nguyen, D. Perino, A. Sarfaraz, C. Yuan, M. Leddige, J. McCall, X. Moua, J. Salmon

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引用次数: 8

摘要

本文描述了一种创新的设计和建模方法，用于开发具有高达每秒1.6千兆字节数据信令带宽的高性能存储器总线。数据信号以每秒800兆比特的传输速率运行。时钟频率为400mhz，信号边缘过渡时间为200ps。由于涉及到极高的频率，必须优化整个系统的电气性能。按照本文提出的方法，模拟结果与实测结果之间获得了良好的相关性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Physical layer design of a 1.6 GB/s DRAM bus

This paper describes an innovative design and modeling methodology for development of a high performance memory bus with data signaling bandwidth of up to 1.6 gigabytes per second. Data signals operate at 800 megabits per second transfer rate. The clock frequency is 400 MHz and the signal edge transition time is 200 ps. Due to the extremely high frequencies involved, overall system electrical performance must be optimized. By following the methodology outlined in this paper, good correlation was obtained between simulated and measured results.

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IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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