RF interconnect for multi-Gbit/sec board-level clock distribution

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819188

Woonghwan Ryu, Hyungsoo Kim, Seungyoung Ahn, Namhoon Kim, Baekkyu Choi, Joungho Kim

引用次数: 2

Abstract

We newly propose a multi-Gbit/sec clock distribution scheme to achieve minimized skew and jitter using RF interconnects. The proposed RF clock distribution scheme has successfully demonstrated less than 22 ps skew and less than 3 ps jitter at 2 GHz.

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用于多gbit /sec板级时钟分配的射频互连

我们提出了一种多gbit /s的时钟分配方案，利用射频互连实现最小的歪斜和抖动。所提出的射频时钟分配方案在2ghz下成功地证明了小于22ps的倾斜和小于3ps的抖动。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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