Simultaneous switch noise and power plane bounce for CMOS technology

Abstract

The simultaneous switch noise (SSN) problem has traditionally been thought of as an inductance problem. When many drivers on a Si chip switch at the same time, current crowds into the chip ground or V/sub dd/ inductance. Ground bounce occurs proportional to the inductance in the ground or V/sub dd/ lead and the rate of change of current. This line of thinking has been effective at solving SSN problems for lead frame packages. However, packaging has progressed to packages with power and ground planes. Package traces behave more like transmission lines with impedance and delay rather than lumped inductors. The signal waveform rise and fall times are so fast that an edge may fit within the package. Wire bonds have been replaced by solder bumps and peripheral leads have been replaced by solder balls. The new structures may have less than 1% of the inductance of the packages in use just a few years ago. Capacitive and resistive elements have been added to inductance matrices to account for the package time delay and losses, but the number of circuit elements in an SSN analysis and the increased number of simultaneously switching drivers have resulted in large, complex simulation runs that require much CPU time and computer resources. It has become harder to find meaningful model to hardware correlation for large SSN problems. It is time to consider a radically new approach to simulating the SSN problem. This paper looks at treatment of the SSN problem as a power plane bounce problem.