Precise chip and package 3D capacitance simulations of realistic interconnects using a general purpose FEM-tool

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819205

A. Hieke

引用次数: 1

Abstract

This paper describes on- and off-chip 3D capacitance simulations utilizing the ANSYS-Multiphysics/sup TM/ general purpose FEM system extended with an APDL macro for capacitance simulations. This facilitates the use of the advanced 3D capabilities of ANSYS/sup TM/ to generate, edit and visualize realistically shaped 3D structures.

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精确的芯片和封装三维电容模拟现实的互连使用通用fem工具

本文描述了利用ANSYS-Multiphysics/sup TM/通用有限元系统扩展APDL宏进行电容仿真的片上和片外三维电容仿真。这有助于使用ANSYS/sup TM/的先进3D功能来生成，编辑和可视化逼真形状的3D结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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