Interconnect limits on gigascale integration

Summary form only given. From the inception of microelectronics in 1959 until the early 1990s, transistors dominated both IC performance and cost, while interconnects were of secondary importance. In recent years, this hegemony has largely dissipated. Interconnects have become critical determinants of IC performance and cost. The nature of this shift can be illustrated by the fact that for late 1980s 1 /spl mu/m technology, the intrinsic switching delay of an unloaded MOSFET approaches 10 ps while 1 mm interconnect response time is approximately 1 ps, but for early 2000 0.1 /spl mu/m technology, intrinsic MOSFET delay decreases to about 1 ps, while 1 mm interconnect response time increases to 100 ps. The latency of a 1 mm interconnect devolves from one decade faster to two decades slower than transistor delay. Concurrent with this signal wiring dilemma, clock frequency is increasing by 100/spl times/ placing stringent new demands on the chip clock distribution network interconnects. Supply current is increasing by 60/spl times/ while supply voltage scales downward by 5/spl times/, imposing a huge new burden on the power distribution network interconnects. Maximum total wire length per chip increases by 50/spl times/, and chip-to-package I/O interconnect count increases by 10-20/spl times/. Early 21st century opportunities for GSI will thus be governed by an interconnect dominated hierarchy of theoretical and practical limits whose five levels are codified as fundamental, material, device, circuit and system. Systematic exploration of this hierarchy of limits reveals salient opportunities to address the interconnect problem.