在Power4测试芯片上的噪声测量

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412) Pub Date : 1999-10-25 DOI:10.1109/EPEP.1999.819186

A. Haridass, N. James, B. McCredie

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引用次数: 0

摘要

本文介绍了在Power4测试芯片上测量的片内噪声及其对芯片上时钟和逻辑电路性能的影响。总结了模内去耦电容对片内噪声的影响。Power4测试芯片采用0.1 /spl mu/m有效通道长度，7金属层Cu, 1.5 V CMOS绝缘体上硅技术制作。测试芯片的设计是为了证明技术的可行性，并为设计1 GHz微处理器的芯片和电路设计方法提供便利。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Noise measurements on Power4 Test chip

This paper describes on-chip noise measured on the Power4 Test chip and its impact on the performance of clock and logic circuitry on the chip. It also summarizes the effect of on-module decoupling capacitors on the on-chip noise. The Power4 Test chip was fabricated in 0.1 /spl mu/m effective channel length, 7 metal layer Cu, 1.5 V CMOS silicon-on-insulator technology. The test chip was designed to demonstrate technology feasibility and to facilitate chip and circuit design methodologies for the design of a 1 GHz microprocessor.

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IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

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