Power distribution modeling and decoupling of multilayer printed circuit board

Abstract

Determining the proper number and value of decoupling capacitors for boards/cards is always a challenging issue for board/card designers. Lack of proper analysis leads to either conservative or aggressive design. This paper presents a methodology for determining the right number and location of decoupling capacitors for a card/board through detailed board modeling. An example has been provided to demonstrate the effect of decoupling capacitors in reducing induced dI/dt noise for a multilayer CPU card with PowerPCT/sup TM/ processor used in IBM's RS/6000 machine.