Noise measurements on Power4 Test chip

Abstract

This paper describes on-chip noise measured on the Power4 Test chip and its impact on the performance of clock and logic circuitry on the chip. It also summarizes the effect of on-module decoupling capacitors on the on-chip noise. The Power4 Test chip was fabricated in 0.1 /spl mu/m effective channel length, 7 metal layer Cu, 1.5 V CMOS silicon-on-insulator technology. The test chip was designed to demonstrate technology feasibility and to facilitate chip and circuit design methodologies for the design of a 1 GHz microprocessor.