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Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.最新文献

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The effects of nitrogen and silicon profile on high-k MOSFET performance and Bias Temperature Instability 氮和硅分布对高k MOSFET性能和偏置温度不稳定性的影响
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345486
C. Choi, C. Kang, C. Kang, R. Choi, H. Cho, Y.H. Kim, S. Rhee, M. Akbar, J.C. Lee
{"title":"The effects of nitrogen and silicon profile on high-k MOSFET performance and Bias Temperature Instability","authors":"C. Choi, C. Kang, C. Kang, R. Choi, H. Cho, Y.H. Kim, S. Rhee, M. Akbar, J.C. Lee","doi":"10.1109/VLSIT.2004.1345486","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345486","url":null,"abstract":"Nitrogen profile has been modulated by inserting Si layer into HfO/sub x/N/sub y/. In this paper, the effects of nitrogen and silicon on MOSFET performance and BTI (Bias Temperature Instability) characteristics have been investigated. Nitrogen incorporation enhanced V/sub TH/ shift for both PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability). However, BTI degradation is significantly suppressed by the Si insertion. This improvement can be attributed to the reduction of oxide bulk trapped as well as interface trapped charge generation resulting from the insertion of Si layer.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129456253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping 等离子体掺杂制备的超低成本高性能65nm CMOS器件
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345465
F. Lallement, B. Duriez, A. Grouillet, F. Arnaud, B. Tavel, F. Wacquant, P. Stolk, M. Woo, Y. Erokhin, J. Scheuer, L. Godet, J. Weeman, D. Distaso, D. Lenoble
{"title":"Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping","authors":"F. Lallement, B. Duriez, A. Grouillet, F. Arnaud, B. Tavel, F. Wacquant, P. Stolk, M. Woo, Y. Erokhin, J. Scheuer, L. Godet, J. Weeman, D. Distaso, D. Lenoble","doi":"10.1109/VLSIT.2004.1345465","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345465","url":null,"abstract":"N-type and p-type Plasma Doping (PLAD) process have been developed for fabricating the ultra-shallow junctions (USJ) needed for the 65nm CMOS technology. For the first time, the strong benefit of PLAD compared to ultra-low energy implantations for fabricating sub-25nm USJ is demonstrated when standard activation technique is used. Such plasma-doped USJ were successfully integrated into a conventional 65nm CMOS architecture (no offset spacers, low ramp-rate spike annealing <75/spl deg/C/s) for the Source-Drain Extensions (SDE) doping. Transistors drive currents of 720 /spl mu/A//spl mu/m and 330 /spl mu/A//spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/=0.9V, I/sub off/=100 nA/ /spl mu/m. In addition, junction leakage current was significantly improved (>1 decade) and junction capacitance was reduced by 15% for NMOS.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 78nm 6F/sup 2/ DRAM technology for multigigabit densities 78nm 6F/sup 2/ DRAM技术，可实现千兆位密度
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345374
F. Fishburn, B. Busch, J. Dale, D. Hwang, R. Lane, T. McDaniel, S. Southwick, R. Turi, H. Wang, L. Tran
{"title":"A 78nm 6F/sup 2/ DRAM technology for multigigabit densities","authors":"F. Fishburn, B. Busch, J. Dale, D. Hwang, R. Lane, T. McDaniel, S. Southwick, R. Turi, H. Wang, L. Tran","doi":"10.1109/VLSIT.2004.1345374","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345374","url":null,"abstract":"This paper discusses a manufacturable 6F/sup 2/ DRAM technology at a 78nm half-pitch feature size that results in the smallest DRAM cell size (0.036 /spl mu/m/sup 2/) to date. The novel 6F/sup 2/ cell design utilizes line/space patterning and self-aligned etches to improve process margin. An MINI capacitor that employs composite high-k dielectric materials is integrated into the process. Tungsten-clad WL and BL reduce parasitics and noise to make this 6F/sup 2/ technology suitable for 2Gb-4Gb density DRAM with a competitive die size for volume production.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133046869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
B/sub 2/H/sub 6/ plasma doping with "in-situ He pre-amorphization" B/sub 2/H/sub 6/等离子体掺杂“原位He预非晶化”
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345466
Y. Sasaki, C. Jin, H. Tamura, B. Mizuno, R. Higaki, T. Satoh, K. Majima, H. Sauddin, K. Takagi, S. Ohmi, K. Tsutsui, H. Iwai
{"title":"B/sub 2/H/sub 6/ plasma doping with \"in-situ He pre-amorphization\"","authors":"Y. Sasaki, C. Jin, H. Tamura, B. Mizuno, R. Higaki, T. Satoh, K. Majima, H. Sauddin, K. Takagi, S. Ohmi, K. Tsutsui, H. Iwai","doi":"10.1109/VLSIT.2004.1345466","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345466","url":null,"abstract":"Plasma doping process to reduce sheet resistance (Rs) keeping shallow junction depth (Xj) was demonstrated. In-situ Helium pre-amorphization (He-PA) was introduced to plasma doping (PD) method. High dose and ultra-shallow as-doped profiles were optimized by adjusting B/sub 2/H/sub 6/ PD conditions. The optical absorption rate in the amorphous layer and Xj was controlled by the He-PA conditions. Advantage of these new techniques to form ultra-shallow p/sup +/-n junction were verified by flash lamp annealing (FLA) and laser annealing (All Solid-State Green Laser Annealing: ASLA) for the first time. Excellent results on Rs, Xj and abruptness of profiles were obtained.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131352613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
On the defect generation and low voltage extrapolation of Q/sub BD/ in SiO/sub 2//HfO/sub 2/ stacks SiO/ sub2 //HfO/ sub2 /堆中Q/sub / BD/的缺陷产生及低压外推
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345440
R. Degraeve, F. Crupi, D. Kwak, G. Groeseneken
{"title":"On the defect generation and low voltage extrapolation of Q/sub BD/ in SiO/sub 2//HfO/sub 2/ stacks","authors":"R. Degraeve, F. Crupi, D. Kwak, G. Groeseneken","doi":"10.1109/VLSIT.2004.1345440","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345440","url":null,"abstract":"The purpose of this paper is to demonstrate that at least a part of the initially present traps is indistinguishable from the electrically generated traps favouring the first interpretation. With this interpretation, we observe on our stack a trap generation threshold below which no degradation occurs, resulting in a virtually infinite Q/sub BD/ at low voltage. This optimistic result is, however, countered by the fact that the pre-stress traps dominate I/sub G/ at low V/sub G/ and limit the yield.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115030530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications 用于模拟/混合信号/射频电路应用的最先进的NMOS和SiGe HBT器件的比较
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345492
K. Kuhn, R. Basco, D. Becher, M. Hattendorf, P. Packan, I. Post, P. Vandervoorn, I. Young
{"title":"A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications","authors":"K. Kuhn, R. Basco, D. Becher, M. Hattendorf, P. Packan, I. Post, P. Vandervoorn, I. Young","doi":"10.1109/VLSIT.2004.1345492","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345492","url":null,"abstract":"RF CMOS performance from a 90nm derivative communications process technology is compared to SiGe BJT performance. NMOS performance at f/sub T//f/sub max/ = 209/248 GHz (70nm) and f/sub T//f/sub max/ = 166/277 GHz (80nm) with F/sub min/ at 0.3 dB (2GHz) and 0.6 dB (10GHz) suggests there is no major reason to implement SiGe HBTs BiCMOS in an integrated communications process.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"32 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128277740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance 一种具有极高性能的新型sub- 50nm多桥通道MOSFET (MBCFET)
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345478
S. Lee, E. Yoon, Sung-min Kim, C. Oh, Ming Li, Jeong-Dong Choi, K. Yeo, Min-Sang Kim, H. Cho, Sung-Hwan Kim, Dong-Won Kim, Donggun Park, Kinam Kim
{"title":"A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance","authors":"S. Lee, E. Yoon, Sung-min Kim, C. Oh, Ming Li, Jeong-Dong Choi, K. Yeo, Min-Sang Kim, H. Cho, Sung-Hwan Kim, Dong-Won Kim, Donggun Park, Kinam Kim","doi":"10.1109/VLSIT.2004.1345478","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345478","url":null,"abstract":"We demonstrate highly manufacturable sub-50 nm MBCFET with the I/sub on/ of 4.26 mA/ /spl mu/m at V/sub DD/ = 1.2V, which is the best performance ever reported. This excellent performance of the MBCFET is resulted from the vertically stacked channels and enhanced mobility. It has been fabricated on bulk Si substrate by using the multiple epitaxial growth of SiGe/Si/SiGe/Si layers and damascene gate process. It has structural and electrical merits in scaling and process integration.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134177096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologies 采用先进集成技术的高可靠性和大批量生产的FRAM嵌入式智能卡
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345445
H. Joo, Y.J. Song, H.H. Kim, S.K. Kang, J. Park, Y. Kang, E. Y. Kang, S.Y. Lee, H. Jeong, Kinam Kim
{"title":"Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologies","authors":"H. Joo, Y.J. Song, H.H. Kim, S.K. Kang, J. Park, Y. Kang, E. Y. Kang, S.Y. Lee, H. Jeong, Kinam Kim","doi":"10.1109/VLSIT.2004.1345445","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345445","url":null,"abstract":"We developed FRAM embedded smartcard in which FRAM replace EEPROM and SRAM to improve the read/write cycle time and endurance of data memories in smartcard. Highly reliable sensing window for FRAM embedded smartcard was achieved by advanced integration technologies such as novel capacitor technology, multi-level encapsulating barrier layer (EBL) technology, and optimal inter-metallic dielectrics (IMD) technology.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134330393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Low cost 65nm CMOS platform for Low Power & General Purpose applications 低成本65nm CMOS平台，适用于低功耗和通用应用
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345363
F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. Dejonghe, M. Broekaart, V. Vachellerie, R. Bianchi, B. Borot, T. Devoivre, N. Bicais, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, M. Woo
{"title":"Low cost 65nm CMOS platform for Low Power & General Purpose applications","authors":"F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. Dejonghe, M. Broekaart, V. Vachellerie, R. Bianchi, B. Borot, T. Devoivre, N. Bicais, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, M. Woo","doi":"10.1109/VLSIT.2004.1345363","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345363","url":null,"abstract":"A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 /spl mu/m/sup 2/ bit-cells with 240mV of SNM and 35 /spl mu/A of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 /spl mu/A/ /spl mu/m and 400 /spl mu/A/ /spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/ = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. /spl mu/m) and analog voltage gain factor (G/sub m//G/sub d/>2000 for L = 10 /spl mu/m) at the leading edge for this process technology. NBTI criteria at 125/spl deg/C for both LP and GP transistors are presented and characterized at overdrive conditions.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116586135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
MRAM with novel shaped cell using synthetic anti-ferromagnetic free layer 采用合成抗铁磁自由层的新型异形单元MRAM
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345371
Y. Ha, J. Lee, H. Kim, J. Bae, S.C. Oh, K. Nam, S.O. Park, N. Lee, H. Kang, U. Chung, J. Moon
{"title":"MRAM with novel shaped cell using synthetic anti-ferromagnetic free layer","authors":"Y. Ha, J. Lee, H. Kim, J. Bae, S.C. Oh, K. Nam, S.O. Park, N. Lee, H. Kang, U. Chung, J. Moon","doi":"10.1109/VLSIT.2004.1345371","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345371","url":null,"abstract":"Magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) using synthetic anti-ferromagnetic (SAF) free layers of various shapes has been developed. SAF free layers show the predominance in the scalability compared with a conventional single free layer. It is also revealed that a novel shaped MTJ with a SAF free layer has a remarkably large writing margin.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"527 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123448126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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