K. Yeo, C. Oh, Sung-min Kim, Min-Sang Kim, Chang-Sub Lee, S. Lee, Ming Li, H. Cho, E. Yoon, Sung-Hwan Kim, J. Choe, Dong-Won Kim, Donggun Park, Kinam Kim
{"title":"80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)","authors":"K. Yeo, C. Oh, Sung-min Kim, Min-Sang Kim, Chang-Sub Lee, S. Lee, Ming Li, H. Cho, E. Yoon, Sung-Hwan Kim, J. Choe, Dong-Won Kim, Donggun Park, Kinam Kim","doi":"10.1109/VLSIT.2004.1345375","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345375","url":null,"abstract":"An 80 nm 512M DDR DRAM with partially-insulated cell array transistor (PiCAT) was fabricated. Si/SiGe epitaxial growth and selective SiGe etch process were used to form PiOX (Partially-Insulating OXide) under source and drain of the cell transistor. Using these technologies, partial-SOI (Silicon-On-Insulator) structure could be realized with excellent structural and electrical advantages on bulk Si wafer. Self-limited shallow junction under source/drain and halo doping effect at the channel region were formed by PiOX. With PiCAT, junction leakage current and SCE (Short Channel Effect) were reduced, and excellent data retention time was obtained.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Cho, B. Lim, J. Kim, S.S. Kim, K. Kim, B.J. Lee, G. Bae, N. Lee, S.H. Kim, K. Koh, H. Kang, M. Seo, S.W. Kim, S.H. Hwang, D.Y. Lee, M.C. Kim, S. Chae, S. Seo, C.W. Kim
{"title":"Full integration and characterization of Localized ONO Memory (LONOM) for embedded flash technology","authors":"I. Cho, B. Lim, J. Kim, S.S. Kim, K. Kim, B.J. Lee, G. Bae, N. Lee, S.H. Kim, K. Koh, H. Kang, M. Seo, S.W. Kim, S.H. Hwang, D.Y. Lee, M.C. Kim, S. Chae, S. Seo, C.W. Kim","doi":"10.1109/VLSIT.2004.1345502","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345502","url":null,"abstract":"We have successfully integrated 8M bits Localized ONO Memory (LONOM) for the embedded nonvolatile memory using 0.13um standard logic process with 5-level Cu metallization. which has a small cell size of 0.276UM and the simplest cell array structure. Without any special algorithm, the localized storage layer of the LONOM can satisfy the essential features for an embedded memory solution, such as low program current. disturb-free read operation and good endurance characteristics. The read speed is as high as 60MHz at V/sub cc/=0.9V, 85/spl deg/C and the current consumption is lower than 5mA at Vcc = 1.4V.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130464705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ueki, M. Narihiro, H. Ohtake, M. Tagami, M. Tada, F. Ito, Y. Harada, M. Abe, N. Inoue, K. Arai, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, M. Hiroi, M. Sekine, Y. Hayashi
{"title":"Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs","authors":"M. Ueki, M. Narihiro, H. Ohtake, M. Tagami, M. Tada, F. Ito, Y. Harada, M. Abe, N. Inoue, K. Arai, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, M. Hiroi, M. Sekine, Y. Hayashi","doi":"10.1109/VLSIT.2004.1345393","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345393","url":null,"abstract":"Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nm/sup /spl phi//-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a \"DD pore seal\" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with k/sub eff/ /spl sim/3.0 is applicable especially for the 65nm-node, low-power ASICs.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123844807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Shiraishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Kohno, T. Chikyo, H. Kitajima, T. Arikado
{"title":"Physics in Fermi level pinning at the polySi/Hf-based high-k oxide interface","authors":"K. Shiraishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Kohno, T. Chikyo, H. Kitajima, T. Arikado","doi":"10.1109/VLSIT.2004.1345421","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345421","url":null,"abstract":"We report that O vacancy (Vo) formation in ionic Hf-based dielectrics and subsequent electron transfer into poly Si gates across the interface, definitely cause substantial flat band (Vfb) shifts especially for p+ gate MISFETs. Our theory can systematically reproduce experiments related to Hf-based dielectrics, and gives a guiding principle towards gate/high-k oxide interface control.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116949341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ohguro, N. Sato, M. Matsuo, K. Kojima, H. Momose, K. Ishimaru, H. Ishiuchi
{"title":"Ultra-thin chip with permalloy film for high performance MS/RF CMOS","authors":"T. Ohguro, N. Sato, M. Matsuo, K. Kojima, H. Momose, K. Ishimaru, H. Ishiuchi","doi":"10.1109/VLSIT.2004.1345490","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345490","url":null,"abstract":"In this paper, we describe the high analog performance of MOSFETs and inductors on 1.7/spl mu/m ultra-thin chip with permalloy film.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116215720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Yamashita, K. Ota, K. Shiga, T. Hayashi, H. Umeda, H. Oda, T. Eimori, M. Inuishi, Y. Ohji, K. Eriguchi, K. Nakanishi, H. Nakaoka, T. Yamada, M. Nakamura, I. Miyanaga, A. Kajiya, M. Kubota, M. Ogura
{"title":"Impact of boron penetration from S/D-extension on gate-oxide reliability for 65-nm node CMOS and beyond","authors":"T. Yamashita, K. Ota, K. Shiga, T. Hayashi, H. Umeda, H. Oda, T. Eimori, M. Inuishi, Y. Ohji, K. Eriguchi, K. Nakanishi, H. Nakaoka, T. Yamada, M. Nakamura, I. Miyanaga, A. Kajiya, M. Kubota, M. Ogura","doi":"10.1109/VLSIT.2004.1345438","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345438","url":null,"abstract":"Nitridation technique of the gate-oxide top surface has been much studied to suppress the boron penetration from the doped gate poly-silicon and proved to be efficient against NBTI degradation. However there is another path for boron to penetrate to gate-oxide from the substrate, where this technique is helpless. We found that boron penetration from the S/D-extension becomes crucial issue on gate leakage and gate-oxide integrity especially for deep sub-micron pMOS, where stress from the sidewall and interlayer dielectrics accelerates to deteriorate those gate-oxide characteristics. We demonstrate that nitridation after gate etching is very efficient to control this new degradation mode. We also propose the totally-optimized transistor structure for nMOS and pMOS, which shows sufficient electrical property and reliability for low operational power (LOP) and low standby power (LSTP) of 65-nm node and beyond.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"9 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125246654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C.H. Lee, J. Yoon, C. Lee, H.M. Yang, K.N. Kim, T.Y. Kim, H. Kang, Y. Ahn, Donggun Park, Kinam Kim
{"title":"Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond","authors":"C.H. Lee, J. Yoon, C. Lee, H.M. Yang, K.N. Kim, T.Y. Kim, H. Kang, Y. Ahn, Donggun Park, Kinam Kim","doi":"10.1109/VLSIT.2004.1345434","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345434","url":null,"abstract":"In this paper, a highly manufacturable 512M FinFET DRAM with novel body tied FinFET cell array transistor on bulk Si substrate has been successfully integrated and the characteristics were compared with RCAT (Recess Channel Array Transistor) and planar cell array transistor DRAM for the first time. We also propose the NWL (Negative Word Line) scheme with low channel doping body tied FinFET for a highly manufacturable FinFET DRAM for sub 60nm technology node.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121693520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Anil, A. Veloso, S. Kubicek, T. Schram, E. Augendre, J. de Marneffe, K. Devriendt, A. Lauwers, S. Brus, K. Henson, S. Biesemans
{"title":"Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications","authors":"K. Anil, A. Veloso, S. Kubicek, T. Schram, E. Augendre, J. de Marneffe, K. Devriendt, A. Lauwers, S. Brus, K. Henson, S. Biesemans","doi":"10.1109/VLSIT.2004.1345472","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345472","url":null,"abstract":"We have fabricated fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics for the first time. We demonstrate that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs. For nMOS devices, a 5 orders of magnitude reduction in short channel sub-threshold leakage is obtained with similar drive current compared to the poly gate devices. In addition, the FUSI process does not degrade the hysterisis nor the dielectric breakdown. This result makes FUSI on high-K a strong candidate for scaled low power technologies.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121986802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Chidambaram, B. A. Smith, L. Hall, H. Bu, S. Chakravarthi, Y. Kim, A. Samoilov, A. Kim, P.J. Jones, R. B. Irwin, M.J. Kim, A. Rotondaro, C. Machala, D. T. Grider
{"title":"35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS","authors":"P. Chidambaram, B. A. Smith, L. Hall, H. Bu, S. Chakravarthi, Y. Kim, A. Samoilov, A. Kim, P.J. Jones, R. B. Irwin, M.J. Kim, A. Rotondaro, C. Machala, D. T. Grider","doi":"10.1109/VLSIT.2004.1345386","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345386","url":null,"abstract":"Results from the best reported PMOS transistor at a 37 nm gate length (Lg) built on a process with a recessed SiGe epitaxial layer are discussed. The process details include successful integration of SiGe at the drain extension (DE) location. A highly compressive SiGe layer, in close proximity to the channel, results in large hole mobility improvements. HRTEM based lattice parameter extractions confirm the compressive strain in the channel. In situ doped B in SiGe can be activated to a higher degree than implanted B in bulk Si resulting in further improvements from the lower DE resistance. Both changes combine to give an unprecedented 35% PMOS performance improvement. Process and device simulations that predict the observed parametric behavior quantitatively isolate the improvements to be /spl sim/ 28% from stress and 7% from DE resistance improvement.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"75 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132871122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Hirano, T. Yamaguchi, K. Sekine, M. Takayanagi, K. Eguchi, Y. Tsunashima, H. Satake
{"title":"Significant role of cold carriers for dielectric breakdown in HfSiON","authors":"I. Hirano, T. Yamaguchi, K. Sekine, M. Takayanagi, K. Eguchi, Y. Tsunashima, H. Satake","doi":"10.1109/VLSIT.2004.1345441","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345441","url":null,"abstract":"Dielectric breakdown mechanisms in HfSiON were thoroughly investigated by utilizing the substrate hot carrier injection. It was found that the total hole fluence (Q/sub p/) dose not dominate the breakdown in HfSiON. Furthermore, it was experimentally clarified that the injected electrons into HfSiON have the significant role for the breakdown, irrespective of their potential energy. This result strongly suggests that the roles of injected cold electrons in HfSiON are remarkably different from those in SiO/sub 2/ and SiON.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134255650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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