80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)

Abstract

An 80 nm 512M DDR DRAM with partially-insulated cell array transistor (PiCAT) was fabricated. Si/SiGe epitaxial growth and selective SiGe etch process were used to form PiOX (Partially-Insulating OXide) under source and drain of the cell transistor. Using these technologies, partial-SOI (Silicon-On-Insulator) structure could be realized with excellent structural and electrical advantages on bulk Si wafer. Self-limited shallow junction under source/drain and halo doping effect at the channel region were formed by PiOX. With PiCAT, junction leakage current and SCE (Short Channel Effect) were reduced, and excellent data retention time was obtained.