B. Doris, Y. Zhang, D. Fried, J. Beintner, O. Dokumaci, W. Natzle, H. Zhu, D. Boyd, J. Holt, J. Petrus, J. Yates, T. Dyer, P. Saunders, M. Steen, E. Nowak, M. Ieong
{"title":"A Simplified Hybrid Orientation Technology (SHOT) for high performance CMOS","authors":"B. Doris, Y. Zhang, D. Fried, J. Beintner, O. Dokumaci, W. Natzle, H. Zhu, D. Boyd, J. Holt, J. Petrus, J. Yates, T. Dyer, P. Saunders, M. Steen, E. Nowak, M. Ieong","doi":"10.1109/VLSIT.2004.1345408","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345408","url":null,"abstract":"A new concept in high performance VLSI called Simplified Hybrid Orientation Technology (SHOT) is introduced. This novel process flow creates circuits with independently oriented surface channels for pMOS and nMOS by integrating FinFETs with planar Ultra-Thin SOI (UTSOI) MOSFETs for the first time. The unique CMOS structure enables high mobility surface channel orientation for both devices. The SHOT scheme is also capable of producing PDSOI devices on the same chip. pFinFET drive current is among the best results reported (810 /spl mu/A//spl mu/m at V/sub dd/ = 1.2V).","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114805299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Motoyoshi, I. Yamamura, W. Ohtsuka, M. Shouji, H. Yamagishi, M. Nakamura, H. Yamada, K. Tai, T. Kikutani, T. Sagara, K. Moriyama, H. Mori, C. Fukamoto, M. Watanabe, R. Hachino, H. Kano, K. Bessho, H. Narisawa, M. Hosomi, N. Okazaki
{"title":"A study for 0.18 /spl mu/m high-density MRAM","authors":"M. Motoyoshi, I. Yamamura, W. Ohtsuka, M. Shouji, H. Yamagishi, M. Nakamura, H. Yamada, K. Tai, T. Kikutani, T. Sagara, K. Moriyama, H. Mori, C. Fukamoto, M. Watanabe, R. Hachino, H. Kano, K. Bessho, H. Narisawa, M. Hosomi, N. Okazaki","doi":"10.1109/VLSIT.2004.1345370","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345370","url":null,"abstract":"In this paper, we study to reduce the switching dispersion and improve 0/1 separation of Magnetic Tunnel Junction (MTJ) elements in order to realize high density MRAM. Various kinds of MTJ sizes and shapes have been evaluated and conclude that in ellipse like shape pattern aspect ratio more than 2 is enough for reproducing and reliable switching characteristics. As regards the reading characteristics, the combination of the optimized MTJ pattern and process makes 21.4 sigma separation between high and low resistance states. In further study of the relation between MTJ shapes and switching distribution, we found a \"Saturn\" shaped MTJ has best switching behavior. Also the toggle mode MRAM is evaluated and its effectiveness for high speed programming is confirmed.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130992682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Tsunoda, A. Sato, H. Tashiro, K. Ohira, T. Nakanishi, H. Tanaka, Y. Arimoto
{"title":"Ultra-high speed Direct Tunneling Memory (DTM) for embedded RAM applications","authors":"K. Tsunoda, A. Sato, H. Tashiro, K. Ohira, T. Nakanishi, H. Tanaka, Y. Arimoto","doi":"10.1109/VLSIT.2004.1345447","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345447","url":null,"abstract":"Direct Tunneling Memory (DTM) with ultra-thin tunnel oxide and novel depleted floating gate (FG) has been demonstrated for embedded RAM applications. Fast programming (<10ns) at low voltage, together with its excellent charge retention (>10s) and large threshold voltage difference (>1.3V), has been achieved by utilizing the band bending at the FG/oxide interface in charge retention period. The depleted FG is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. As a consequence, newly proposed DTM is a promising candidate for cost-effective and scalable embedded RAM instead of a conventional embedded DRAM.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Iwai, A. Oishi, T. Sanuki, Y. Takegawa, T. Komoda, Y. Morimasa, K. Ishimaru, M. Takayanagi, K. Eguchi, D. Matsushita, K. Muraoka, K. Sunouchi, T. Noguchi
{"title":"45nm CMOS platform technology (CMOS6) with high density embedded memories","authors":"M. Iwai, A. Oishi, T. Sanuki, Y. Takegawa, T. Komoda, Y. Morimasa, K. Ishimaru, M. Takayanagi, K. Eguchi, D. Matsushita, K. Muraoka, K. Sunouchi, T. Noguchi","doi":"10.1109/VLSIT.2004.1345364","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345364","url":null,"abstract":"This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are compatible with 0.069um/sup 2/ trench capacitor DRAM and 0.247um/sup 2/ 6Tr.SRAM embedded memories.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"140 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123142247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Hwang, J. Ho, Y. Liu, J.J. Shen, W. Chen, D. Chen, W. Liao, Y. S. Hsieh, W. Lin, C. Hsu, H. Lin, M.F. Lu, A. Kuo, S. Huang-Lu, H. Tang, D. Chen, W. Shiau, K. Liao, S. Sun
{"title":"Symmetrical 45nm PMOS on [110] substrate with excellent S/D extension distribution and mobility enhancement","authors":"J. Hwang, J. Ho, Y. Liu, J.J. Shen, W. Chen, D. Chen, W. Liao, Y. S. Hsieh, W. Lin, C. Hsu, H. Lin, M.F. Lu, A. Kuo, S. Huang-Lu, H. Tang, D. Chen, W. Shiau, K. Liao, S. Sun","doi":"10.1109/VLSIT.2004.1345410","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345410","url":null,"abstract":"For the first time, 45 nm PMOS devices on the only 4-fold symmetry zone of [110] surface substrates were demonstrated with excellent diffusion control in the S/D extension region. A 30% drive current enhancement was observed compared to devices on conventional (100) substrates with <110> channel. Resistance to gate oxide interface generation induced by charge injection stress is increased by 2 times. Improved 1/f noise characteristics were also observed on [110] surface substrates, especially when devices operate at the linear region.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115036385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiongfei Yu, Chunxiang Zhu, X.P. Wang, M. Li, A. Chin, A. Du, W.D. Wang, D. Kwong
{"title":"High mobility and excellent electrical stability of MOSFETs using a novel HfTaO gate dielectric","authors":"Xiongfei Yu, Chunxiang Zhu, X.P. Wang, M. Li, A. Chin, A. Du, W.D. Wang, D. Kwong","doi":"10.1109/VLSIT.2004.1345422","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345422","url":null,"abstract":"In this work, we developed a novel Hf-based gate dielectric for MOSFETs with TaN metal gate. By incorporating Ta into HfO/sub 2/ films, significant improvements were achieved in contrast to pure HfO/sub 2/: (1) the dielectric crystallization temperature is increased up to 1000/spl deg/C; (2) interface states density (D/sub it/) is reduced by one order of magnitude; (3) electron peak mobility is enhanced by more than two times; (4) charge trapping and threshold voltage shift is reduced by 20 times, greatly prolonging the device lifetime; (5) negligible sub-threshold swing and G/sub m/ variations under constant voltage stress (CVS).","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115607198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Shino, I. Higashi, K. Fujita, T. Ohsawa, Y. Minami, T. Yamada, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, A. Nitayama
{"title":"Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applications","authors":"T. Shino, I. Higashi, K. Fujita, T. Ohsawa, Y. Minami, T. Yamada, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, A. Nitayama","doi":"10.1109/VLSIT.2004.1345435","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345435","url":null,"abstract":"A novel FBC with 25nm-thick BOX (buried oxide) structure has been developed. A feature of new FBC is scalability in the case of thinner SOI, which promises embedded DRAM on SOI in future generations. Using 96Kbit array, the pause time distribution of FBC is demonstrated for the first time. Due to simplified structure, pause time variation of new FBC is significantly suppressed compared with conventional FBC.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117145308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Ryu, Woo-Young Chung, You-Jean Jang, Yong-Jun Lee, Hyung-Seok Jung, C. Oh, Hee-Sung Kang, Young-Wug Kim
{"title":"Fully working 1.10 /spl mu/m/sup 2/ embedded 6T-SRAM technology with high-k gate dielectric device for ultra low power applications","authors":"H. Ryu, Woo-Young Chung, You-Jean Jang, Yong-Jun Lee, Hyung-Seok Jung, C. Oh, Hee-Sung Kang, Young-Wug Kim","doi":"10.1109/VLSIT.2004.1345380","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345380","url":null,"abstract":"Ultra low power 1.10 /spl mu/m/sup 2/ 6T-SRAM chip with HfO/sub 2/-Al/sub 2/O/sub 3/ gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO/sub 2/-Al/sub 2/O/sub 3/ film was 17/spl Aring/ and gate leakage current density was 1600-times lower than that of the oxynitride. Current performance of 90nm gate length NFET and PFET with HfO/sub 2/-Al/sub 2/O/sub 3/ were 335 and 115 /spl mu/A/ /spl mu/m, while Ioff were 0.9 and 2.0pA/ /spl mu/m, respectively. SNM value of 1.10 /spl mu/m/sup 2/ 6T-SRAM bit cell was 340mV at Vdd = 1.2V. Stand-by current of the SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd = 1.2V.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126170370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Torii, T. Aoyama, S. Kamiyama, Y. Tamura, S. Miyazaki, H. Kitajima, T. Arikado
{"title":"Dielectric breakdown mechanism of HfSiON/SiO/sub 2/ gate dielectric","authors":"K. Torii, T. Aoyama, S. Kamiyama, Y. Tamura, S. Miyazaki, H. Kitajima, T. Arikado","doi":"10.1109/VLSIT.2004.1345423","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345423","url":null,"abstract":"The breakdown mechanism of HfSiON/SiO/sub 2/ gate stacks is discussed, based on studies of the band diagram, carrier separation and charge pumping measurements. We found that both holes and electrons contribute to BD and therefore the combination of the stress polarity and the device type should be chosen carefully to evaluate the reliability.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125950747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Maeda, You-Seung Jin, J. Choi, S. Oh, Hyun-Woo Lee, Jae-yoon Yoo, Min-Chul Sun, J. Ku, K. Lee, Su-gon Bae, S. Kang, Jeong-Hwan Yang, Young-Wug Kim, K. Suh
{"title":"Impact of mechanical stress engineering on flicker noise characteristics","authors":"S. Maeda, You-Seung Jin, J. Choi, S. Oh, Hyun-Woo Lee, Jae-yoon Yoo, Min-Chul Sun, J. Ku, K. Lee, Su-gon Bae, S. Kang, Jeong-Hwan Yang, Young-Wug Kim, K. Suh","doi":"10.1109/VLSIT.2004.1345417","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345417","url":null,"abstract":"Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"35 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130780112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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