K. Tsunoda, A. Sato, H. Tashiro, K. Ohira, T. Nakanishi, H. Tanaka, Y. Arimoto
{"title":"Ultra-high speed Direct Tunneling Memory (DTM) for embedded RAM applications","authors":"K. Tsunoda, A. Sato, H. Tashiro, K. Ohira, T. Nakanishi, H. Tanaka, Y. Arimoto","doi":"10.1109/VLSIT.2004.1345447","DOIUrl":null,"url":null,"abstract":"Direct Tunneling Memory (DTM) with ultra-thin tunnel oxide and novel depleted floating gate (FG) has been demonstrated for embedded RAM applications. Fast programming (<10ns) at low voltage, together with its excellent charge retention (>10s) and large threshold voltage difference (>1.3V), has been achieved by utilizing the band bending at the FG/oxide interface in charge retention period. The depleted FG is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. As a consequence, newly proposed DTM is a promising candidate for cost-effective and scalable embedded RAM instead of a conventional embedded DRAM.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345447","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Direct Tunneling Memory (DTM) with ultra-thin tunnel oxide and novel depleted floating gate (FG) has been demonstrated for embedded RAM applications. Fast programming (<10ns) at low voltage, together with its excellent charge retention (>10s) and large threshold voltage difference (>1.3V), has been achieved by utilizing the band bending at the FG/oxide interface in charge retention period. The depleted FG is also effective to suppress the degradation of program/erase speed caused by the gate re-oxidation process. As a consequence, newly proposed DTM is a promising candidate for cost-effective and scalable embedded RAM instead of a conventional embedded DRAM.