Fully working 1.10 /spl mu/m/sup 2/ embedded 6T-SRAM technology with high-k gate dielectric device for ultra low power applications

Abstract

Ultra low power 1.10 /spl mu/m/sup 2/ 6T-SRAM chip with HfO/sub 2/-Al/sub 2/O/sub 3/ gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO/sub 2/-Al/sub 2/O/sub 3/ film was 17/spl Aring/ and gate leakage current density was 1600-times lower than that of the oxynitride. Current performance of 90nm gate length NFET and PFET with HfO/sub 2/-Al/sub 2/O/sub 3/ were 335 and 115 /spl mu/A/ /spl mu/m, while Ioff were 0.9 and 2.0pA/ /spl mu/m, respectively. SNM value of 1.10 /spl mu/m/sup 2/ 6T-SRAM bit cell was 340mV at Vdd = 1.2V. Stand-by current of the SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd = 1.2V.