具有高密度嵌入式存储器的45纳米CMOS平台技术(CMOS6)

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI:10.1109/VLSIT.2004.1345364

M. Iwai, A. Oishi, T. Sanuki, Y. Takegawa, T. Komoda, Y. Morimasa, K. Ishimaru, M. Takayanagi, K. Eguchi, D. Matsushita, K. Muraoka, K. Sunouchi, T. Noguchi

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引用次数: 13

摘要

本文介绍了第一个45nm节点CMOS技术(CMOS6)，优化了Vdd, EOT和BEOL参数。为了使该技术从高性能CPU应用到移动应用，提出了三组核心器件，分别兼容0.069um/sup 2/沟槽电容DRAM和0.247um/sup 2/ 6Tr。SRAM嵌入式存储器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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45nm CMOS platform technology (CMOS6) with high density embedded memories

This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are compatible with 0.069um/sup 2/ trench capacitor DRAM and 0.247um/sup 2/ 6Tr.SRAM embedded memories.

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Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

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