Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.最新文献_第10页

Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates 采用多晶硅栅极和FUSI栅极的fet V/sub / hf基栅极栈的系统研究

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345383

E. Cartier, V. Narayanan, E. Gusev, P. Jamison, B. Linder, M. Steen, K. Chan, M. Frank, N. Bojarczuk, M. Copel, S. Cohen, S. Zafar, A. Callegari, M. Gribelyuk, M. Chudzik, C. Cabral, R. Carruthers, C. D'Emic, J. Newbury, D. Lacey, S. Guha, R. Jammy

引用次数: 25

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes 增强的90nm高性能技术，通过简单的工艺改变，从应力和迁移率的增加中获得了强大的性能改进

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345456

R. Khamankar, H. Bu, C. Bowen, S. Chakravarthi, P. Chidambaram, M. Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J.P. Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall, H. Alshareef, A. Varghese, A. Gurba, V. Ukraintsev, B. Rathsack, J. Deloach, J. Tran, C. Kaneshige, M. Somervell, S. Aur, C. Machala, T. Grider

{"title":"An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes","authors":"R. Khamankar, H. Bu, C. Bowen, S. Chakravarthi, P. Chidambaram, M. Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J.P. Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall, H. Alshareef, A. Varghese, A. Gurba, V. Ukraintsev, B. Rathsack, J. Deloach, J. Tran, C. Kaneshige, M. Somervell, S. Aur, C. Machala, T. Grider","doi":"10.1109/VLSIT.2004.1345456","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345456","url":null,"abstract":"In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA//spl mu/m. An industry leading 90nm technology CV/I of 0.61 ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12/spl Aring/ EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123882710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO/sub 2/) gate dielectric 高k (HfO/sub 2/)栅极介电介质的亚100nm TaSiN金属栅全耗尽SOI器件的性能和可靠性

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345420

A. Thean, A. Vandooren, S. Kalpat, Y. Du, I. To, J. Hughes, T. Stephens, B. Goolsby, T. White, A. Barr, L. Mathew, M. Huang, S. Egley, M. Zavala, D. Eades, K. Sphabmixay, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, D. Pham, R. Rai, S. Murphy, B. Nguyen, B. White, A. Duvallet, T. Dao, J. Mogab

引用次数: 7

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell 45纳米节点平面- soi技术，0.296 /spl mu/m/sup 2/ 6T-SRAM单元

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345362

Fu-Liang Yang, Cheng-Chuan Huang, Chien-Chao Huang, Tang-Xuan Chung, Hou-Yu Chen, Chang-Yun Chang, Hung-Wei Chen, Di-Hong Lee, Sheng-Da Liu, Kuang-Hsin Chen, Cheng-Kuo Wen, Shui-Ming Cheng, Chang-Ta Yang, Li-Wei Kung, Chiu-Lien Lee, Y. Chou, Fu-Jye Liang, Lin-Hung Shiu, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, T. Gau, Ping-Wei Wang, B. Chan, P. Hsu, J. Shieh, S. Fung, C. H. Diaz, C. Wu, Y. See, B.J. Lin, M. Liang, J. Sun, C. Hu

引用次数: 10

Selectively-formed high mobility SiGe-on-Insulator pMOSFETs with Ge-rich strained surface channels using local condensation technique 利用局部冷凝技术，选择性形成具有富锗应变表面通道的高迁移率绝缘子上硅基晶体管

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345477

T. Tezuka, S. Nakaharai, Y. Moriyama, N. Sugiyama, S. Takagi

引用次数: 32

Engineering of voltage nonlinearity in high-k MIM capacitor for analog/mixed-signal ICs 模拟/混合信号集成电路用高k MIM电容的电压非线性工程

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345489

Sun Jung Kim, B. Cho, M. Li, S. Ding, M. Yu, Chunxiang Zhu, A. Chin, D. Kwong

引用次数: 21

Reliability robustness of 65nm BEOL Cu damascene interconnects using porous CVD low-k dielectrics with k = 2.2 使用k = 2.2的多孔CVD低k介电介质的65nm BEOL Cu damascene互连的可靠性稳健性

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 1900-01-01 DOI: 10.1109/VLSIT.2004.1345396

K.C. Lin, Y.C. Lu, L.P. Li, B.T. Chen, H. Chang, H. Lu, S. Jeng, S. Jang, M. Liang

{"title":"Reliability robustness of 65nm BEOL Cu damascene interconnects using porous CVD low-k dielectrics with k = 2.2","authors":"K.C. Lin, Y.C. Lu, L.P. Li, B.T. Chen, H. Chang, H. Lu, S. Jeng, S. Jang, M. Liang","doi":"10.1109/VLSIT.2004.1345396","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345396","url":null,"abstract":"Reliability concerns over the applications of porous low-k dielectrics for Cu dual damascene (DD) interconnects have been dismissed with novel film formation methods, patterning approaches and structure designs. Results showed that the BEOL time dependent dielectric breakdown (BEOL TDDB) performance of interconnects built using porous CVD LK's with k=2.2 and pore size /spl sim/2.8nm were not comprised with film pore integrity retained to have TDDB T/sub 63/ predicted to be 1 /spl times/ 10/sup 9/ yrs at 0.3 MV/cm and 125/spl deg/C. Further investigations also revealed that the impacts of weak mechanical and poor thermal properties associated with the LK material on its interconnect electromigration and stress migration performances can be demolished through various interface engineering with EM lifetimes of 0.12 /spl mu/m Cu lines or 0.13 /spl mu/m vias at 1 MA/cm/sup 2/ and 110/spl deg/C longer than 400k hrs or 150k hrs, and SM failure rate = 0 (>100% Re shift) for vias on all test structures after thermal annealing at 150/spl deg/C for 500 hrs.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131042761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0