Fu-Liang Yang, Cheng-Chuan Huang, Chien-Chao Huang, Tang-Xuan Chung, Hou-Yu Chen, Chang-Yun Chang, Hung-Wei Chen, Di-Hong Lee, Sheng-Da Liu, Kuang-Hsin Chen, Cheng-Kuo Wen, Shui-Ming Cheng, Chang-Ta Yang, Li-Wei Kung, Chiu-Lien Lee, Y. Chou, Fu-Jye Liang, Lin-Hung Shiu, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, T. Gau, Ping-Wei Wang, B. Chan, P. Hsu, J. Shieh, S. Fung, C. H. Diaz, C. Wu, Y. See, B.J. Lin, M. Liang, J. Sun, C. Hu
{"title":"45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell","authors":"Fu-Liang Yang, Cheng-Chuan Huang, Chien-Chao Huang, Tang-Xuan Chung, Hou-Yu Chen, Chang-Yun Chang, Hung-Wei Chen, Di-Hong Lee, Sheng-Da Liu, Kuang-Hsin Chen, Cheng-Kuo Wen, Shui-Ming Cheng, Chang-Ta Yang, Li-Wei Kung, Chiu-Lien Lee, Y. Chou, Fu-Jye Liang, Lin-Hung Shiu, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, T. Gau, Ping-Wei Wang, B. Chan, P. Hsu, J. Shieh, S. Fung, C. H. Diaz, C. Wu, Y. See, B.J. Lin, M. Liang, J. Sun, C. Hu","doi":"10.1109/VLSIT.2004.1345362","DOIUrl":null,"url":null,"abstract":"The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.
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