发布求助
文献互助 智能选刊 最新文献

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.最新文献

筛选
英文 中文
110nm NROM technology for code and data flash products 110nm NROM技术用于代码和数据闪存产品
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345402
J. Willer, C. Ludwig, J. Deppe, C. Kleint, S. Riedel, J.-U. Sachse, M. Krause, R. Mikalo, E. S. Kamienski, S. Parascandola, T. Mikolajick, Jan-Malte Fischer, M. Isler, K. Kuesters, I. Bloom, A. Shapir, E. Lusky, B. Eitan
{"title":"110nm NROM technology for code and data flash products","authors":"J. Willer, C. Ludwig, J. Deppe, C. Kleint, S. Riedel, J.-U. Sachse, M. Krause, R. Mikalo, E. S. Kamienski, S. Parascandola, T. Mikolajick, Jan-Malte Fischer, M. Isler, K. Kuesters, I. Bloom, A. Shapir, E. Lusky, B. Eitan","doi":"10.1109/VLSIT.2004.1345402","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345402","url":null,"abstract":"A novel NROM generation with a bit size of 0,043 /spl mu/m/sup 2//bit at a 110nm design rule is introduced. The concept features mainstream CMOS type cell devices in conjunction with a metal contact based virtual ground array architecture. The new technology node serves both advanced code flash products and file storage memories up to 2 Gbit/die.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133685284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices 基于栅极长度低于10 nm的平面体CMOS器件的hp22 nm节点低工作功率(LOP)技术
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345407
N. Yasutake, K. Ohuchi, M. Fujiwara, K. Adachi, A. Hokazono, K. Kojima, N. Aoki, H. Suto, T. Watanabe, T. Morooka, H. Mizuno, S. Magoshi, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, M. Ohmura, K. Miyano, H. Yamada, H. Tomita, D. Matsushita, K. Muraoka, S. Inaba, M. Takayanagi, K. Ishimaru, H. Ishiuchi
{"title":"A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices","authors":"N. Yasutake, K. Ohuchi, M. Fujiwara, K. Adachi, A. Hokazono, K. Kojima, N. Aoki, H. Suto, T. Watanabe, T. Morooka, H. Mizuno, S. Magoshi, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, M. Ohmura, K. Miyano, H. Yamada, H. Tomita, D. Matsushita, K. Muraoka, S. Inaba, M. Takayanagi, K. Ishimaru, H. Ishiuchi","doi":"10.1109/VLSIT.2004.1345407","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345407","url":null,"abstract":"High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133549280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application 基于选择性应变氮化盖的应力记忆技术(SMT)在sub-65nm高性能应变硅器件中的应用
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345390
Chien-Hao Chen, T. Lee, T. Hou, C.L. Chen, C. Chen, J.W. Hsu, K. Cheng, Y. Chiu, H. Tao, Y. Jin, C. H. Diaz, S. Chen, M. Liang
{"title":"Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application","authors":"Chien-Hao Chen, T. Lee, T. Hou, C.L. Chen, C. Chen, J.W. Hsu, K. Cheng, Y. Chiu, H. Tao, Y. Jin, C. H. Diaz, S. Chen, M. Liang","doi":"10.1109/VLSIT.2004.1345390","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345390","url":null,"abstract":"An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process. it was found to gain additional /spl sim/10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process. which is a promising local strain approach for sub-65nm CMOS application.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123275909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 111
Effects of barrier height (/spl Phi//sub B/) and the nature of bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology 势垒高度(/spl Phi//sub B/)和双层结构性质对双金属栅极(Ru & Ru- ta合金)高k电介质可靠性的影响
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345439
Y.H. Kim, R. Choi, R. Jha, J. Lee, V. Misra, J.C. Lee
{"title":"Effects of barrier height (/spl Phi//sub B/) and the nature of bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology","authors":"Y.H. Kim, R. Choi, R. Jha, J. Lee, V. Misra, J.C. Lee","doi":"10.1109/VLSIT.2004.1345439","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345439","url":null,"abstract":"In this work, we present the effects of barrier height on the reliability of HfO/sub 2/ with dual metal gate technology in terms of Weibull slope, soft breakdown characteristics, defect generation rate, critical defect density and charge-to-breakdown. It was found that the lower Weibull slope of high-k dielectrics (compared to SiO/sub 2/) is partially attributed to the lower barrier height of high-k dielectrics which in turn results in larger current increase. Thus, defect generation rate increases and charge-to-break down decreases, while critical defect density remains constant. In addition, it has been found that there is distinct bi-modal defect generation rate for high-k/SiO/sub 2/ stack. Two-step breakdown process was clearly observed; and Weibull slope of soft breakdown (1/sup st/ breakdown) shows lower /spl beta/ value compared to that of hard breakdown (2/sup nd/ breakdown). Soft breakdown characteristics were dependent on the barrier heights. The bi-modal defect generations are believed to be resulted from the breakdown in interface and bulk layer.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124917831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dual workfunction fully silicided metal gates 双工作功能全硅化金属闸门
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345469
C. Cabral, J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozłowski, R. Carruthers, R. Jammy
{"title":"Dual workfunction fully silicided metal gates","authors":"C. Cabral, J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozłowski, R. Carruthers, R. Jammy","doi":"10.1109/VLSIT.2004.1345469","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345469","url":null,"abstract":"Fully silicided (FUSI), dual workfunction (WF), Ni monosilicide metal gates are demonstrated using Sb predoped polySi for setting the nFET WF and for the first time a combination of Al predoped polySi and a Ni(Pt) alloy silicide for the pFET WF. The combination of the Sb and Al predoped polySi along with the Ni(Pt)Si, allow for WFs spanning the Si band gap to within 0.2 eV of the band edges. With this large WF range the FUSI, dual WF, NiSi process is applicable for both high performance and low power CMOS applications. It is shown that the Al and Sb predoped polySi and the Ni(Pt)Si alloy have leakage currents equivalent to NiSi formed from intrinsic polySi. A fundamental voiding problem in the formation of CoSi/sub 2/ metal gates is also demonstrated, indicating the superiority of the NiSi gates.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121163381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A new vertically stacked poly-Si MOSFET with partially depleted SOI operation for densely integrated SoC applications 一种新的垂直堆叠多晶硅MOSFET，具有部分耗尽的SOI操作，用于密集集成的SoC应用
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345498
H. Matsuoka, T. Mine, K. Nakazato, M. Moniwa, Y. Takahashi, M. Matsuoka, H. Chakihara, A. Fujimoto, K. Okuyama
{"title":"A new vertically stacked poly-Si MOSFET with partially depleted SOI operation for densely integrated SoC applications","authors":"H. Matsuoka, T. Mine, K. Nakazato, M. Moniwa, Y. Takahashi, M. Matsuoka, H. Chakihara, A. Fujimoto, K. Okuyama","doi":"10.1109/VLSIT.2004.1345498","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345498","url":null,"abstract":"Vertical transistors take up less area than conventional planar CMOS devices and are thus promising as a means for increased densities of integration. Most of the vertical MOSFET structures proposed so far, however, require sophisticated processing which is incompatible with conventional CMOS processes. In this paper, we propose the use of a vertical poly-Si pMOSFET for SoC applications; this structure is easily stacked on bulk nMOS, eliminating the need for an n-well region and significantly reducing chip Size. The formation of poly-Si grain boundaries across the active channels of poly-Si MOSFETs means that these devices tend to exhibit poor performance in the form of large threshold-voltage fluctuations and large subthreshold swings. A vertical poly-Si transistor that operates with a partially depleted SOI structure and shows excellent DC characteristics has been developed as a solution to these problems. The impact of this new vertical pMOS structure on 6T-SRAM is also demonstrated.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126911928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications 用于高密度应用的亚40nm三栅极电荷捕获非易失性存储单元
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345504
M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, L. Risch
{"title":"Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications","authors":"M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, L. Risch","doi":"10.1109/VLSIT.2004.1345504","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345504","url":null,"abstract":"Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L/sub G/ = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129049214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
55nm high mobility SiGe(:C) pMOSFETs with HfO/sub 2/ gate dielectric and TiN metal gate for advanced CMOS 55nm高迁移率SiGe(:C) pmosfet，具有HfO/sub /栅极介质和TiN金属栅极，用于先进的CMOS
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345382
O. Weber, F. Ducroquet, T. Ernst, F. Andrieu, J. Damlencourt, J. Hartmann, B. Guillaumot, A. Papon, H. Dansas, L. Brevard, A. Toffoli, P. Besson, F. Martin, Y. Morand, S. Deleonibus
{"title":"55nm high mobility SiGe(:C) pMOSFETs with HfO/sub 2/ gate dielectric and TiN metal gate for advanced CMOS","authors":"O. Weber, F. Ducroquet, T. Ernst, F. Andrieu, J. Damlencourt, J. Hartmann, B. Guillaumot, A. Papon, H. Dansas, L. Brevard, A. Toffoli, P. Besson, F. Martin, Y. Morand, S. Deleonibus","doi":"10.1109/VLSIT.2004.1345382","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345382","url":null,"abstract":"For the first time, MOS transistors with compressively strained SiGe(:C) channel, metal gate and high-k dielectric are demonstrated down to 55nm gate length. SiGe(:C) surface channel pMOSFETs with HfO/sub 2/ gate dielectric exhibit a 10/sup 4/ gate leakage reduction and a 65% mobility enhancement at high transverse effective field (1MV/cm) when compared to the universal SiO/sub 2//Si reference. With such a thin Equivalent Oxide Thickness (EOT= 16-18/spl Aring/), this represents the best gate leakage/mobility trade-off ever published.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122244209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A model for negative bias temperature instability (NBTI) in oxide and high /spl kappa/ pFETs 13/spl times/-C6D8C7F5F2 氧化物和高/spl kappa/ pfet负偏置温度不稳定性(NBTI)模型13/spl倍/-C6D8C7F5F2
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345483
S. Zafar, B. Lee, J. Stathis, A. Callegari, T. Ning
{"title":"A model for negative bias temperature instability (NBTI) in oxide and high /spl kappa/ pFETs 13/spl times/-C6D8C7F5F2","authors":"S. Zafar, B. Lee, J. Stathis, A. Callegari, T. Ning","doi":"10.1109/VLSIT.2004.1345483","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345483","url":null,"abstract":"A model for the negative bias temperature instability (NBTI) is proposed. Unlike previous empirical models, this model is derived from physics principles. The model attributes NBTI to de-passivation of SiO/sub 2//Si interface and its two distinguishing features are: application of statistical mechanics to calculate depassivated site density increase and the assumption that the hydrogen diffusion is dispersive. The model is verified using new and published NBTI data for SiO/sub 2//poly, SiON/W and HfO/sub 2//W pFETs. A comparison between high /spl kappa/ and conventional oxide is made.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124432379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node 基于氮化硅封盖层的65纳米技术节点MOSFET电流驱动优化
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345389
S. Pidin, T. Mori, R. Nakamura, T. Saiki, R. Tanabe, S. Satoh, M. Kase, K. Hashimoto, T. Sugii
{"title":"MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node","authors":"S. Pidin, T. Mori, R. Nakamura, T. Saiki, R. Tanabe, S. Satoh, M. Kase, K. Hashimoto, T. Sugii","doi":"10.1109/VLSIT.2004.1345389","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345389","url":null,"abstract":"NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and 1V supply voltage fabricated NMOSFET delivers 1.00mA/ /spl mu/m drive current for off-state current of 40nA/ /spl mu/m and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability. Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132495132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信