N. Yasutake, K. Ohuchi, M. Fujiwara, K. Adachi, A. Hokazono, K. Kojima, N. Aoki, H. Suto, T. Watanabe, T. Morooka, H. Mizuno, S. Magoshi, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, M. Ohmura, K. Miyano, H. Yamada, H. Tomita, D. Matsushita, K. Muraoka, S. Inaba, M. Takayanagi, K. Ishimaru, H. Ishiuchi
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A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices
High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.
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