110nm NROM technology for code and data flash products

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI:10.1109/VLSIT.2004.1345402

J. Willer, C. Ludwig, J. Deppe, C. Kleint, S. Riedel, J.-U. Sachse, M. Krause, R. Mikalo, E. S. Kamienski, S. Parascandola, T. Mikolajick, Jan-Malte Fischer, M. Isler, K. Kuesters, I. Bloom, A. Shapir, E. Lusky, B. Eitan

引用次数: 5

Abstract

A novel NROM generation with a bit size of 0,043 /spl mu/m/sup 2//bit at a 110nm design rule is introduced. The concept features mainstream CMOS type cell devices in conjunction with a metal contact based virtual ground array architecture. The new technology node serves both advanced code flash products and file storage memories up to 2 Gbit/die.

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110nm NROM技术用于代码和数据闪存产品

介绍了一种在110nm设计规则下，位元尺寸为0.043 /spl mu/m/sup / 2/ bit的新型NROM。该概念采用主流CMOS型电池器件，结合基于金属触点的虚拟地阵架构。新技术节点既支持先进的代码闪存产品，也支持高达2gbit /die的文件存储存储器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

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