Y.H. Kim, R. Choi, R. Jha, J. Lee, V. Misra, J.C. Lee
{"title":"势垒高度(/spl Phi//sub B/)和双层结构性质对双金属栅极(Ru & Ru- ta合金)高k电介质可靠性的影响","authors":"Y.H. Kim, R. Choi, R. Jha, J. Lee, V. Misra, J.C. Lee","doi":"10.1109/VLSIT.2004.1345439","DOIUrl":null,"url":null,"abstract":"In this work, we present the effects of barrier height on the reliability of HfO/sub 2/ with dual metal gate technology in terms of Weibull slope, soft breakdown characteristics, defect generation rate, critical defect density and charge-to-breakdown. It was found that the lower Weibull slope of high-k dielectrics (compared to SiO/sub 2/) is partially attributed to the lower barrier height of high-k dielectrics which in turn results in larger current increase. Thus, defect generation rate increases and charge-to-break down decreases, while critical defect density remains constant. In addition, it has been found that there is distinct bi-modal defect generation rate for high-k/SiO/sub 2/ stack. Two-step breakdown process was clearly observed; and Weibull slope of soft breakdown (1/sup st/ breakdown) shows lower /spl beta/ value compared to that of hard breakdown (2/sup nd/ breakdown). Soft breakdown characteristics were dependent on the barrier heights. The bi-modal defect generations are believed to be resulted from the breakdown in interface and bulk layer.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Effects of barrier height (/spl Phi//sub B/) and the nature of bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology\",\"authors\":\"Y.H. Kim, R. Choi, R. Jha, J. Lee, V. Misra, J.C. Lee\",\"doi\":\"10.1109/VLSIT.2004.1345439\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we present the effects of barrier height on the reliability of HfO/sub 2/ with dual metal gate technology in terms of Weibull slope, soft breakdown characteristics, defect generation rate, critical defect density and charge-to-breakdown. It was found that the lower Weibull slope of high-k dielectrics (compared to SiO/sub 2/) is partially attributed to the lower barrier height of high-k dielectrics which in turn results in larger current increase. Thus, defect generation rate increases and charge-to-break down decreases, while critical defect density remains constant. In addition, it has been found that there is distinct bi-modal defect generation rate for high-k/SiO/sub 2/ stack. Two-step breakdown process was clearly observed; and Weibull slope of soft breakdown (1/sup st/ breakdown) shows lower /spl beta/ value compared to that of hard breakdown (2/sup nd/ breakdown). Soft breakdown characteristics were dependent on the barrier heights. The bi-modal defect generations are believed to be resulted from the breakdown in interface and bulk layer.\",\"PeriodicalId\":297052,\"journal\":{\"name\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2004.1345439\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345439","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effects of barrier height (/spl Phi//sub B/) and the nature of bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technology
In this work, we present the effects of barrier height on the reliability of HfO/sub 2/ with dual metal gate technology in terms of Weibull slope, soft breakdown characteristics, defect generation rate, critical defect density and charge-to-breakdown. It was found that the lower Weibull slope of high-k dielectrics (compared to SiO/sub 2/) is partially attributed to the lower barrier height of high-k dielectrics which in turn results in larger current increase. Thus, defect generation rate increases and charge-to-break down decreases, while critical defect density remains constant. In addition, it has been found that there is distinct bi-modal defect generation rate for high-k/SiO/sub 2/ stack. Two-step breakdown process was clearly observed; and Weibull slope of soft breakdown (1/sup st/ breakdown) shows lower /spl beta/ value compared to that of hard breakdown (2/sup nd/ breakdown). Soft breakdown characteristics were dependent on the barrier heights. The bi-modal defect generations are believed to be resulted from the breakdown in interface and bulk layer.