用于高密度应用的亚40nm三栅极电荷捕获非易失性存储单元

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI:10.1109/VLSIT.2004.1345504

M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, L. Risch

{"title":"用于高密度应用的亚40nm三栅极电荷捕获非易失性存储单元","authors":"M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, L. Risch","doi":"10.1109/VLSIT.2004.1345504","DOIUrl":null,"url":null,"abstract":"Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L/sub G/ = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"169 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications\",\"authors\":\"M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, L. Risch\",\"doi\":\"10.1109/VLSIT.2004.1345504\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L/sub G/ = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.\",\"PeriodicalId\":297052,\"journal\":{\"name\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"volume\":\"169 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2004.1345504\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 24

摘要

首次制备了极短栅极长度(L/sub / = 30 ~ 80nm)的全耗尽三栅极氧化氮氧化物(ONO)晶体管存储单元。该器件表现出非常好的电特性，并已成功地优化了高密度应用。提出了一种nand型阵列结构，并给出了集成问题的解决方案。此外，高分辨率扫描扩展电阻显微镜已被用于可视化三栅极存储器件的导通状态。

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Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications

Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L/sub G/ = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.

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来源期刊

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

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