E. Cartier, V. Narayanan, E. Gusev, P. Jamison, B. Linder, M. Steen, K. Chan, M. Frank, N. Bojarczuk, M. Copel, S. Cohen, S. Zafar, A. Callegari, M. Gribelyuk, M. Chudzik, C. Cabral, R. Carruthers, C. D'Emic, J. Newbury, D. Lacey, S. Guha, R. Jammy
{"title":"采用多晶硅栅极和FUSI栅极的fet V/sub / hf基栅极栈的系统研究","authors":"E. Cartier, V. Narayanan, E. Gusev, P. Jamison, B. Linder, M. Steen, K. Chan, M. Frank, N. Bojarczuk, M. Copel, S. Cohen, S. Zafar, A. Callegari, M. Gribelyuk, M. Chudzik, C. Cabral, R. Carruthers, C. D'Emic, J. Newbury, D. Lacey, S. Guha, R. Jammy","doi":"10.1109/VLSIT.2004.1345383","DOIUrl":null,"url":null,"abstract":"The flatband/threshold voltages (V/sub fb//V/sub t/) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO/sub 2/ at poly-Si deposition temperatures is identified as the root cause for the poor V/sub fb//V/sub t/ control. No improvement in V/sub t/ control is obtained by engineering physically closed Si/sub 3/N/sub 4/ barrier layers on HfO/sub 2/. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V/sub fb//V/sub t/ shifts are observed with HfO/sub 2/. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al/sub 2/O/sub 3/ cap layers on silicates.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates\",\"authors\":\"E. Cartier, V. Narayanan, E. Gusev, P. Jamison, B. Linder, M. Steen, K. Chan, M. Frank, N. Bojarczuk, M. Copel, S. Cohen, S. Zafar, A. Callegari, M. Gribelyuk, M. Chudzik, C. Cabral, R. Carruthers, C. D'Emic, J. Newbury, D. Lacey, S. Guha, R. Jammy\",\"doi\":\"10.1109/VLSIT.2004.1345383\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The flatband/threshold voltages (V/sub fb//V/sub t/) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO/sub 2/ at poly-Si deposition temperatures is identified as the root cause for the poor V/sub fb//V/sub t/ control. No improvement in V/sub t/ control is obtained by engineering physically closed Si/sub 3/N/sub 4/ barrier layers on HfO/sub 2/. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V/sub fb//V/sub t/ shifts are observed with HfO/sub 2/. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al/sub 2/O/sub 3/ cap layers on silicates.\",\"PeriodicalId\":297052,\"journal\":{\"name\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2004.1345383\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345383","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates
The flatband/threshold voltages (V/sub fb//V/sub t/) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO/sub 2/ at poly-Si deposition temperatures is identified as the root cause for the poor V/sub fb//V/sub t/ control. No improvement in V/sub t/ control is obtained by engineering physically closed Si/sub 3/N/sub 4/ barrier layers on HfO/sub 2/. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V/sub fb//V/sub t/ shifts are observed with HfO/sub 2/. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al/sub 2/O/sub 3/ cap layers on silicates.
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