高k (HfO/sub 2/)栅极介电介质的亚100nm TaSiN金属栅全耗尽SOI器件的性能和可靠性

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI:10.1109/VLSIT.2004.1345420

A. Thean, A. Vandooren, S. Kalpat, Y. Du, I. To, J. Hughes, T. Stephens, B. Goolsby, T. White, A. Barr, L. Mathew, M. Huang, S. Egley, M. Zavala, D. Eades, K. Sphabmixay, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, D. Pham, R. Rai, S. Murphy, B. Nguyen, B. White, A. Duvallet, T. Dao, J. Mogab

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引用次数: 7

摘要

在本文中，我们报告了具有高k栅极介电介质的亚100nm TaSiN金属栅全耗尽SOI器件的性能和可靠性。强调了完全耗尽和部分耗尽设备之间的性能差异。这也是首次报道了金属/高k器件中电子和空穴迁移率之间独特的不对称退化现象。尽管使用高k介电介质，我们表明这些器件具有优越的可靠性，噪声和模拟电路性能。

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Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO/sub 2/) gate dielectric

In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.

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Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

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