A. Thean, A. Vandooren, S. Kalpat, Y. Du, I. To, J. Hughes, T. Stephens, B. Goolsby, T. White, A. Barr, L. Mathew, M. Huang, S. Egley, M. Zavala, D. Eades, K. Sphabmixay, J. Schaeffer, D. Triyoso, M. Rossow, D. Roan, D. Pham, R. Rai, S. Murphy, B. Nguyen, B. White, A. Duvallet, T. Dao, J. Mogab
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引用次数: 7
Abstract
In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.
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