An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI:10.1109/VLSIT.2004.1345456

R. Khamankar, H. Bu, C. Bowen, S. Chakravarthi, P. Chidambaram, M. Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J.P. Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall, H. Alshareef, A. Varghese, A. Gurba, V. Ukraintsev, B. Rathsack, J. Deloach, J. Tran, C. Kaneshige, M. Somervell, S. Aur, C. Machala, T. Grider

{"title":"An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes","authors":"R. Khamankar, H. Bu, C. Bowen, S. Chakravarthi, P. Chidambaram, M. Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J.P. Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall, H. Alshareef, A. Varghese, A. Gurba, V. Ukraintsev, B. Rathsack, J. Deloach, J. Tran, C. Kaneshige, M. Somervell, S. Aur, C. Machala, T. Grider","doi":"10.1109/VLSIT.2004.1345456","DOIUrl":null,"url":null,"abstract":"In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA//spl mu/m. An industry leading 90nm technology CV/I of 0.61 ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12/spl Aring/ EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345456","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 20

Abstract

In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA//spl mu/m. An industry leading 90nm technology CV/I of 0.61 ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12/spl Aring/ EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.

查看原文本刊更多论文

增强的90nm高性能技术，通过简单的工艺改变，从应力和迁移率的增加中获得了强大的性能改进

在本文中，我们提出了一种高度可制造的高性能90nm技术，该技术具有35nm栅长N和P晶体管的同类最佳性能。独特，但简单和低成本的工艺变化已被用于调节通道应力和植入物的轮廓，以产生增强的性能，而无需额外的掩膜。在1.2V Vdd和60nA//spl mu/m的关断下，nMOS和pMOS晶体管分别获得1193uA/um和587uA/um的高驱动电流。nMOS和pMOS晶体管的90纳米技术CV/I分别为0.61 ps和1.12ps。使用了一种积极缩放的12/spl Aring/ EOT等离子体氮化簇栅介电介质。对工艺条件进行了优化，以获得高驱动电流，良好的Vt滚降控制，同时满足可靠性要求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

自引率

0.00%

发文量