高可靠性，65纳米节点Cu双damascene互连与全多孔sioch (k=2.5)薄膜，用于低功耗asic

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI:10.1109/VLSIT.2004.1345393

M. Ueki, M. Narihiro, H. Ohtake, M. Tagami, M. Tada, F. Ito, Y. Harada, M. Abe, N. Inoue, K. Arai, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, M. Hiroi, M. Sekine, Y. Hayashi

{"title":"高可靠性，65纳米节点Cu双damascene互连与全多孔sioch (k=2.5)薄膜，用于低功耗asic","authors":"M. Ueki, M. Narihiro, H. Ohtake, M. Tagami, M. Tada, F. Ito, Y. Harada, M. Abe, N. Inoue, K. Arai, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, M. Hiroi, M. Sekine, Y. Hayashi","doi":"10.1109/VLSIT.2004.1345393","DOIUrl":null,"url":null,"abstract":"Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nm/sup /spl phi//-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a \"DD pore seal\" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with k/sub eff/ /spl sim/3.0 is applicable especially for the 65nm-node, low-power ASICs.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs\",\"authors\":\"M. Ueki, M. Narihiro, H. Ohtake, M. Tagami, M. Tada, F. Ito, Y. Harada, M. Abe, N. Inoue, K. Arai, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, M. Hiroi, M. Sekine, Y. Hayashi\",\"doi\":\"10.1109/VLSIT.2004.1345393\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nm/sup /spl phi//-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a \\\"DD pore seal\\\" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with k/sub eff/ /spl sim/3.0 is applicable especially for the 65nm-node, low-power ASICs.\",\"PeriodicalId\":297052,\"journal\":{\"name\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2004.1345393\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

在全孔sioch薄膜(k=2.5)中，已经开发出具有180nm/200nm间距线和100nm/sup /spl phi//-过孔的全尺寸缩小的65nm节点Cu双damascene互连(ddi)。介绍了两种新技术，如:(1)低热预算工艺，以确保DDI过孔产率，而不产生Cu团聚;(2)覆盖线沟和过孔的所有侧壁的“DD孔隙密封”，以提高介电可靠性。具有薄Ta/TaN阻隔层的全多孔sioch DDI与多孔刚性混合单大马士革互连(sdi)相比，整体RC产品提高了24%。具有k/sub / /spl sim/3.0的高性价比ddi尤其适用于65nm节点的低功耗asic。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nm/sup /spl phi//-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with k/sub eff/ /spl sim/3.0 is applicable especially for the 65nm-node, low-power ASICs.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

自引率

0.00%

发文量