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Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.最新文献

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65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application 65nm CMOS高速、通用、低功耗晶体管技术，适用于大批量铸造应用
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345411
S. Fung, H. Huang, S.M. Cheng, K. Cheng, S.W. Wang, Y.P. Wang, Y. Yao, C. Chu, S.J. Yang, W. Liang, Y. Leung, C.C. Wu, C. Lin, S. Chang, S. Wu, C. Nieh, C. Chen, T. Lee, Y. Jin, S. Chen, L. Lin, Y. Chiu, H. Tao, C. Fu, S. Jang, K. F. Yu, C. Wang, T. Ong, Y. See, C. H. Diaz, M. Liang, Y.C. Sun
{"title":"65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application","authors":"S. Fung, H. Huang, S.M. Cheng, K. Cheng, S.W. Wang, Y.P. Wang, Y. Yao, C. Chu, S.J. Yang, W. Liang, Y. Leung, C.C. Wu, C. Lin, S. Chang, S. Wu, C. Nieh, C. Chen, T. Lee, Y. Jin, S. Chen, L. Lin, Y. Chiu, H. Tao, C. Fu, S. Jang, K. F. Yu, C. Wang, T. Ong, Y. See, C. H. Diaz, M. Liang, Y.C. Sun","doi":"10.1109/VLSIT.2004.1345411","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345411","url":null,"abstract":"This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127608499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Extended scaling of ultrathin gate oxynitride toward sub-65nm CMOS by optimization of UV photo-oxidation, soft plasma/thermal nitridation & stress enhancement 通过优化紫外光氧化、软等离子体/热氮化和应力增强，将超薄栅氮化氧化物扩展到低于65nm的CMOS
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345464
Chi-Chun Chen, V. Chang, Y. Jin, C. Chen, T. Lee, S. Chen, M. Liang
{"title":"Extended scaling of ultrathin gate oxynitride toward sub-65nm CMOS by optimization of UV photo-oxidation, soft plasma/thermal nitridation & stress enhancement","authors":"Chi-Chun Chen, V. Chang, Y. Jin, C. Chen, T. Lee, S. Chen, M. Liang","doi":"10.1109/VLSIT.2004.1345464","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345464","url":null,"abstract":"A novel UV photo-oxidation (UVPO) is developed for ideal \"atomic-layer oxidation\" with excellent thickness control down to 4/spl Aring/, which is very promising for interfacial layer formation of scaled gate oxynitride and high-k applications. In addition, ultrathin oxynitride (EOT<12/spl Aring/) using a newly-developed low ion-energy nitrogen plasma (30% plasma damage reduction) in combination with thermal nitridation is demonstrated for n/pMOSFET performance optimization. Finally, device performance is further enhanced (+7% of nFET Ion-Ioff by tensile stress with negligible impact on pFET) by mechanical stress modulation from strain contact-etch-stop layer (CESL). The proposed technologies represent an efficient approach to realize ultrathin gate oxynitride toward sub-65nm CMOS production.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124224709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM 革命性的真正三维25F/sup 2/ SRAM技术，具有最小的S/sup 3/(堆叠单晶Si)电池，0.16um/sup 2/，以及用于超高密度SRAM的SSTFT(攻击单晶薄膜晶体管)
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345495
Soon-Moon Jung, J. Jang, W. Cho, J. Moon, K. Kwak, Bonghyun Choi, B. Hwang, H. Lim, Jaehun Jeong, Jonghyuk Kim, Kinam Kim
{"title":"The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM","authors":"Soon-Moon Jung, J. Jang, W. Cho, J. Moon, K. Kwak, Bonghyun Choi, B. Hwang, H. Lim, Jaehun Jeong, Jonghyuk Kim, Kinam Kim","doi":"10.1109/VLSIT.2004.1345495","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345495","url":null,"abstract":"The smallest 25F/sup 2/ SRAM cell size of 0.16um/sup 2/ is realized by S/sup 3/ cell technology and SSTFT with 193nm ArF lithography process. The stacked single-crystal thin film is developed and used for the first time in the SRAM cell to make the SRAM products comparative to the DRAM products in the density and the cost. The load PMOS and pass NMOS transistors are stacked over the planar pull-down NMOS transistors to drastically reduce the cell size. In this study, the dream of truly 3D memory device is achieved by fabricating 64M bit density SRAM.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
A CPU on a plastic film substrate 塑料薄膜衬底上的CPU
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345496
T. Takayama, Y. Ohno, Y. Goto, A. Machida, M. Fujita, J. Maruyama, K. Kato, J. Koyama, S. Yamazaki
{"title":"A CPU on a plastic film substrate","authors":"T. Takayama, Y. Ohno, Y. Goto, A. Machida, M. Fujita, J. Maruyama, K. Kato, J. Koyama, S. Yamazaki","doi":"10.1109/VLSIT.2004.1345496","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345496","url":null,"abstract":"A CPU using a high performance poly-silicon TFT is successfully fabricated on a plastic film substrate by a TFT transfer technology onto a plastic film substrate we developed. No performance degradation by the transfer process was observed, and we confirmed the CPU operation at the frequency of more than 10MHz with a power source voltage 33V.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117144890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Laminated metal gate electrode with tunable work function for advanced CMOS 用于先进CMOS的工作功能可调的层压金属栅电极
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345471
S. H. Bae, W. Bai, H. Wen, S. Mathew, L. Bera, N. Balasubramanian, N. Yamada, M. Li, D. Kwong
{"title":"Laminated metal gate electrode with tunable work function for advanced CMOS","authors":"S. H. Bae, W. Bai, H. Wen, S. Mathew, L. Bera, N. Balasubramanian, N. Yamada, M. Li, D. Kwong","doi":"10.1109/VLSIT.2004.1345471","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345471","url":null,"abstract":"This paper presents a novel technique for tuning the work function of metal gate electrodes. Laminated metal gate electrodes consisting of 1/spl sim/3 ultra thin (/spl sim/10 /spl Aring/) layers of Ta, TaN, Ti, TiN, Hf or HfN and bulk metal nitride gate electrodes were deposited on SiO/sub 2/, HfO/sub 2/ or HfON, followed by RTP annealing to evaluate their thermal stability. Our results show that the work function of the laminated metal gate electrodes is significantly different from their bulk electrodes counterpart. Through lamination, a TiTaN/sub x/ alloy gate is formed which exhibits NMOS compatible work function (4.35 eV) with good thermal stability up to 900/spl deg/C. Laminated metal gates consisting of 3 components exhibit pMOS compatible work function (5,0/spl sim/5.2 eV) after 1000/spl deg/C annealing and this value remains unchanged after subsequent thermal processing. Possible mechanism responsible for work function tuning using laminated gates is discussed.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132475277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Scanrom, a novel non-volatile memory cell storing 9 bits 一种新颖的非易失性存储单元，存储9位
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345401
M. Rosmeulen, J. van Houdt, L. Haspeslagh, K. De Meyer
{"title":"Scanrom, a novel non-volatile memory cell storing 9 bits","authors":"M. Rosmeulen, J. van Houdt, L. Haspeslagh, K. De Meyer","doi":"10.1109/VLSIT.2004.1345401","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345401","url":null,"abstract":"We present a novel non-volatile memory cell based on a dual-gate transistor with an ONO charge-trapping dielectric underneath the drain-side gate. Multiple bits are stored along the width of the device. By contacting the gates from both sides and applying an appropriate bias difference to each, the individual bits are addressed for both reading and writing. We experimentally demonstrate reading and writing of 9 bits in a prototype cell and discuss to possibility of storing an even higher number of bits.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126816981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Device challenges and opportunities 设备挑战与机遇
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345359
C. Hu
{"title":"Device challenges and opportunities","authors":"C. Hu","doi":"10.1109/VLSIT.2004.1345359","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345359","url":null,"abstract":"CMOS technology is facing exciting opportunities and formidable challenges. They include mobility scaling to overcome the speed/power barrier, new gate-stack materials and/or new device structures; to overcome the gate-length/leakage barrier; nonvolatile memory and universal memory to enlarge the market, and containment of costs. CMOS has much more to give in the next two decades, yet it is not too early, especially in universities, to start searching for not-CMOS-like circuit/system architectures that may require non-existing new devices but offer the promise of dramatic reduction in power and cost.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM 通过一次掩模蚀刻工艺形成的0.602 /spl mu/m/sup / 2/的“链状”单元结构
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345446
H. Kanaya, K. Tomioka, T. Matsushita, M. Omura, T. Ozaki, Y. Kumura, Y. Shimojo, T. Morimoto, O. Hidaka, S. Shuto, H. Koyama, Y. Yamada, K. Osari, N. Tokoh, F. Fujisaki, N. Iwabuchi, N. Yamaguchi, T. Watanabe, M. Yabuki, H. Shinomiya, N. Watanabe, E. Itoh, T. Tsuchiya, K. Yamakawa, K. Natori, S. Yamazaki, K. Nakazawa, D. Takashima, S. Shiratake, S. Ohtsuki, Y. Oowaki, I. Kunishima, A. Nitayama
{"title":"A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM","authors":"H. Kanaya, K. Tomioka, T. Matsushita, M. Omura, T. Ozaki, Y. Kumura, Y. Shimojo, T. Morimoto, O. Hidaka, S. Shuto, H. Koyama, Y. Yamada, K. Osari, N. Tokoh, F. Fujisaki, N. Iwabuchi, N. Yamaguchi, T. Watanabe, M. Yabuki, H. Shinomiya, N. Watanabe, E. Itoh, T. Tsuchiya, K. Yamakawa, K. Natori, S. Yamazaki, K. Nakazawa, D. Takashima, S. Shiratake, S. Ohtsuki, Y. Oowaki, I. Kunishima, A. Nitayama","doi":"10.1109/VLSIT.2004.1345446","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345446","url":null,"abstract":"We have successfully developed a 0.602 /spl mu/m/sup 2/ nestled 'Chain' FeRAM cell technology for 64Mbit FeRAM. In the 'Chain' FeRAM a pair of capacitors on a same node can be nestled close to each other A combination of a one mask etching process of ferro-electric capacitors and the nestled structure drastically scaled down the cell size to 0.602 /spl mu/m/sup 2/. The cell size was reduced to 32% of previous work. Signal window of 600 mV was obtained by the nestled 'Chain' FeRAM structure after full integration of three-metal CMOS technology.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114757691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Charge-injection length in silicon nanocrystal memory cells 硅纳米晶存储单元中的电荷注入长度
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345503
T. Osabe, T. Ishii, T. Mine, T. Sano, T. Arigane, T. Fukumura, H. Kurata, S. Saeki, Y. Ikeda, K. Yano
{"title":"Charge-injection length in silicon nanocrystal memory cells","authors":"T. Osabe, T. Ishii, T. Mine, T. Sano, T. Arigane, T. Fukumura, H. Kurata, S. Saeki, Y. Ikeda, K. Yano","doi":"10.1109/VLSIT.2004.1345503","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345503","url":null,"abstract":"We present the first experimental investigation of the lateral charge-injection length for silicon nanocrystal memory cells programmed with source-side injection (SSI). Charge-pumping measurements reveal that the injection length of SSI programming is reducible to 24 nm and suggest the possibility of scaling down the nanocrystal memory for 2-bit/cell operation to the 90-65-nm range of technology nodes.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114983147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High performance CMOSFET technology for 45nm generation 45纳米一代的高性能CMOSFET技术
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI: 10.1109/VLSIT.2004.1345458
A. Oishi, T. Komoda, Y. Morimasa, T. Sanuki, H. Yamasaki, M. Hamaguchi, K. Oouchi, K. Matsuo, T. Iinuma, T. Itoh, Y. Takegawa, M. Iwai, K. Sunouchi, T. Noguchi
{"title":"High performance CMOSFET technology for 45nm generation","authors":"A. Oishi, T. Komoda, Y. Morimasa, T. Sanuki, H. Yamasaki, M. Hamaguchi, K. Oouchi, K. Matsuo, T. Iinuma, T. Itoh, Y. Takegawa, M. Iwai, K. Sunouchi, T. Noguchi","doi":"10.1109/VLSIT.2004.1345458","DOIUrl":"https://doi.org/10.1109/VLSIT.2004.1345458","url":null,"abstract":"High performance CMOSFET process design for 45nm generation is demonstrated. Activation process policy is shown for the first time to achieve high performance source and drain extension (SDE) junction, high gate activation and defect-less source and drain (SD) junction simultaneously for 45nm generation technology. Most serious problem of phosphorus TED is investigated In detail and suppressed by appropriate designing of activation process. Good Vth roll-off and Ion-Ioff characteristics are achieved for 20nm gate MOSFET by utilizing ultra high speed annealing technique, disposable sidewall spacer, phosphorus n+ SD and appropriate designing of activation process.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123196844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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