High performance CMOSFET technology for 45nm generation

Abstract

High performance CMOSFET process design for 45nm generation is demonstrated. Activation process policy is shown for the first time to achieve high performance source and drain extension (SDE) junction, high gate activation and defect-less source and drain (SD) junction simultaneously for 45nm generation technology. Most serious problem of phosphorus TED is investigated In detail and suppressed by appropriate designing of activation process. Good Vth roll-off and Ion-Ioff characteristics are achieved for 20nm gate MOSFET by utilizing ultra high speed annealing technique, disposable sidewall spacer, phosphorus n+ SD and appropriate designing of activation process.