H. Kanaya, K. Tomioka, T. Matsushita, M. Omura, T. Ozaki, Y. Kumura, Y. Shimojo, T. Morimoto, O. Hidaka, S. Shuto, H. Koyama, Y. Yamada, K. Osari, N. Tokoh, F. Fujisaki, N. Iwabuchi, N. Yamaguchi, T. Watanabe, M. Yabuki, H. Shinomiya, N. Watanabe, E. Itoh, T. Tsuchiya, K. Yamakawa, K. Natori, S. Yamazaki, K. Nakazawa, D. Takashima, S. Shiratake, S. Ohtsuki, Y. Oowaki, I. Kunishima, A. Nitayama
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A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAM
We have successfully developed a 0.602 /spl mu/m/sup 2/ nestled 'Chain' FeRAM cell technology for 64Mbit FeRAM. In the 'Chain' FeRAM a pair of capacitors on a same node can be nestled close to each other A combination of a one mask etching process of ferro-electric capacitors and the nestled structure drastically scaled down the cell size to 0.602 /spl mu/m/sup 2/. The cell size was reduced to 32% of previous work. Signal window of 600 mV was obtained by the nestled 'Chain' FeRAM structure after full integration of three-metal CMOS technology.
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