S. Fung, H. Huang, S.M. Cheng, K. Cheng, S.W. Wang, Y.P. Wang, Y. Yao, C. Chu, S.J. Yang, W. Liang, Y. Leung, C.C. Wu, C. Lin, S. Chang, S. Wu, C. Nieh, C. Chen, T. Lee, Y. Jin, S. Chen, L. Lin, Y. Chiu, H. Tao, C. Fu, S. Jang, K. F. Yu, C. Wang, T. Ong, Y. See, C. H. Diaz, M. Liang, Y.C. Sun
{"title":"65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application","authors":"S. Fung, H. Huang, S.M. Cheng, K. Cheng, S.W. Wang, Y.P. Wang, Y. Yao, C. Chu, S.J. Yang, W. Liang, Y. Leung, C.C. Wu, C. Lin, S. Chang, S. Wu, C. Nieh, C. Chen, T. Lee, Y. Jin, S. Chen, L. Lin, Y. Chiu, H. Tao, C. Fu, S. Jang, K. F. Yu, C. Wang, T. Ong, Y. See, C. H. Diaz, M. Liang, Y.C. Sun","doi":"10.1109/VLSIT.2004.1345411","DOIUrl":null,"url":null,"abstract":"This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"44","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345411","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 44
Abstract
This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
