{"title":"SiO/ sub2 //HfO/ sub2 /堆中Q/sub / BD/的缺陷产生及低压外推","authors":"R. Degraeve, F. Crupi, D. Kwak, G. Groeseneken","doi":"10.1109/VLSIT.2004.1345440","DOIUrl":null,"url":null,"abstract":"The purpose of this paper is to demonstrate that at least a part of the initially present traps is indistinguishable from the electrically generated traps favouring the first interpretation. With this interpretation, we observe on our stack a trap generation threshold below which no degradation occurs, resulting in a virtually infinite Q/sub BD/ at low voltage. This optimistic result is, however, countered by the fact that the pre-stress traps dominate I/sub G/ at low V/sub G/ and limit the yield.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"On the defect generation and low voltage extrapolation of Q/sub BD/ in SiO/sub 2//HfO/sub 2/ stacks\",\"authors\":\"R. Degraeve, F. Crupi, D. Kwak, G. Groeseneken\",\"doi\":\"10.1109/VLSIT.2004.1345440\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The purpose of this paper is to demonstrate that at least a part of the initially present traps is indistinguishable from the electrically generated traps favouring the first interpretation. With this interpretation, we observe on our stack a trap generation threshold below which no degradation occurs, resulting in a virtually infinite Q/sub BD/ at low voltage. This optimistic result is, however, countered by the fact that the pre-stress traps dominate I/sub G/ at low V/sub G/ and limit the yield.\",\"PeriodicalId\":297052,\"journal\":{\"name\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2004.1345440\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345440","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the defect generation and low voltage extrapolation of Q/sub BD/ in SiO/sub 2//HfO/sub 2/ stacks
The purpose of this paper is to demonstrate that at least a part of the initially present traps is indistinguishable from the electrically generated traps favouring the first interpretation. With this interpretation, we observe on our stack a trap generation threshold below which no degradation occurs, resulting in a virtually infinite Q/sub BD/ at low voltage. This optimistic result is, however, countered by the fact that the pre-stress traps dominate I/sub G/ at low V/sub G/ and limit the yield.
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