Low cost 65nm CMOS platform for Low Power & General Purpose applications

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. Pub Date : 2004-06-15 DOI:10.1109/VLSIT.2004.1345363

F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. Dejonghe, M. Broekaart, V. Vachellerie, R. Bianchi, B. Borot, T. Devoivre, N. Bicais, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, M. Woo

{"title":"Low cost 65nm CMOS platform for Low Power & General Purpose applications","authors":"F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. Dejonghe, M. Broekaart, V. Vachellerie, R. Bianchi, B. Borot, T. Devoivre, N. Bicais, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, M. Woo","doi":"10.1109/VLSIT.2004.1345363","DOIUrl":null,"url":null,"abstract":"A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 /spl mu/m/sup 2/ bit-cells with 240mV of SNM and 35 /spl mu/A of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 /spl mu/A/ /spl mu/m and 400 /spl mu/A/ /spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/ = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. /spl mu/m) and analog voltage gain factor (G/sub m//G/sub d/>2000 for L = 10 /spl mu/m) at the leading edge for this process technology. NBTI criteria at 125/spl deg/C for both LP and GP transistors are presented and characterized at overdrive conditions.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345363","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 34

Abstract

A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 /spl mu/m/sup 2/ bit-cells with 240mV of SNM and 35 /spl mu/A of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 /spl mu/A/ /spl mu/m and 400 /spl mu/A/ /spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/ = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. /spl mu/m) and analog voltage gain factor (G/sub m//G/sub d/>2000 for L = 10 /spl mu/m) at the leading edge for this process technology. NBTI criteria at 125/spl deg/C for both LP and GP transistors are presented and characterized at overdrive conditions.

查看原文本刊更多论文

低成本65nm CMOS平台，适用于低功耗和通用应用

采用传统设计和低成本CMOS工艺流程，结合应变硅解决方案，开发了采用通用(GP)和低功耗(LP)器件和0.5 /spl mu/m/sup 2/ 6T-SRAM位单元的65nm CMOS平台。在1.2V工作条件下，获得了0.5 /spl mu/m/sup 2/ bit-cell, SNM为240mV, cell电流为35 /spl mu/A。在V/sub dd/ = 1V, Ioff = 100nA/um时，NMOS和PMOS的GP晶体管驱动电流分别为875 /spl mu/A/ /spl mu/m和400 /spl mu/A/ /spl mu/m。采用相同的CMOS流程，首次推导出65nm模拟晶体管参数，显示出Vt匹配(Avt=2.2mV)。/spl mu/m)和模拟电压增益系数(G/sub //G/sub / d/>2000, L = 10 /spl mu/m)在该工艺技术中处于领先地位。提出了LP和GP晶体管在125/spl度/C下的NBTI标准，并在超速条件下进行了表征。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

自引率

0.00%

发文量