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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)最新文献

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A power-efficient voltage-based neural tissue stimulator with energy recovery 具有能量恢复功能的高效电压神经组织刺激器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332677
Shawn K. Kelly, John L. Wyatt
{"title":"A power-efficient voltage-based neural tissue stimulator with energy recovery","authors":"Shawn K. Kelly, John L. Wyatt","doi":"10.1109/ISSCC.2004.1332677","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332677","url":null,"abstract":"A voltage-based neural stimulator for an implant is fabricated in 1.5/spl mu/m CMOS. Wireless power transmission and synchronous rectification allow the use of a set of intermediate voltage supplies. This system achieves power consumption 53% lower than traditional current-source stimulators delivering the same charge to electrodes.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127847852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
100MPackets/s fully self-timed priority queue: FQ 100mppackets /s完全自定时优先队列:FQ
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332638
M. Iwatal, M. Ogura, Y. Ohishi, H. Hayashi, H. Terada
{"title":"100MPackets/s fully self-timed priority queue: FQ","authors":"M. Iwatal, M. Ogura, Y. Ohishi, H. Hayashi, H. Terada","doi":"10.1109/ISSCC.2004.1332638","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332638","url":null,"abstract":"This priority queuing module is integrated as part of QoS functions in a data-driven network processor chip. Since the whole FQ circuit is realized by a fully self-timed folded pipeline, each prioritized 128b packet arriving at 100Mpackets/s is queued and scheduled autonomously in a self-timed manner.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121396523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An SoC with two multimedia DSPs and a RISC core for video compression applications 具有两个多媒体dsp和用于视频压缩应用的RISC核心的SoC
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332728
H. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, Mladen Berekovic, P. Pirsch
{"title":"An SoC with two multimedia DSPs and a RISC core for video compression applications","authors":"H. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, Mladen Berekovic, P. Pirsch","doi":"10.1109/ISSCC.2004.1332728","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332728","url":null,"abstract":"An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm/sup 2/ chip is implemented in a 0.18/spl mu/m 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124251214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process 一个PVT容忍度为0.18MHz至600MHz的90nm CMOS工艺自校准数字锁相环
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332807
J. Lin, B. Haroun, T. Foo, Jin-Sheng Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr, J. Kirkpatric
{"title":"A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process","authors":"J. Lin, B. Haroun, T. Foo, Jin-Sheng Wang, B. Helmick, S. Randall, T. Mayhugh, C. Barr, J. Kirkpatric","doi":"10.1109/ISSCC.2004.1332807","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332807","url":null,"abstract":"This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillator, and start-up calibration, which achieves a constant damping factor and fractional loop bandwidth over a 0.18 MHz to 600 MHz range of output frequencies and PVT conditions, with output jitter less than 0.04 UIPP. The 0.18 mm/sup 2/ chip is implemented in 90 nm CMOS, operates over a 0.7 to 2.4 V power supply range and consumes 1.7 mW at 1 V and 520 MHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131689188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
A 21mW 8b 125MS/s ADC occupying 0.09mm/sup 2/ in 0.13/spl mu/m CMOS 一个21mW 8b 125MS/s ADC，占用0.09mm/sup / / 0.13/spl mu/m CMOS
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332693
J. Mulder, C. Ward, Chi-Hung Lin, D. Kruse, J. Westra, M. Lugthart, E. Arslan, R. van de Plassche, K. Bult, F.M.L. van der Goes
{"title":"A 21mW 8b 125MS/s ADC occupying 0.09mm/sup 2/ in 0.13/spl mu/m CMOS","authors":"J. Mulder, C. Ward, Chi-Hung Lin, D. Kruse, J. Westra, M. Lugthart, E. Arslan, R. van de Plassche, K. Bult, F.M.L. van der Goes","doi":"10.1109/ISSCC.2004.1332693","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332693","url":null,"abstract":"An 8b subranging ADC uses interpolation, averaging, offset compensation and pipelining techniques to accomplish 7.6b ENOB at 125MS/s. The 0.13/spl mu/m CMOS ADC occupies 0.09mm/sup 2/ and consumes 21 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126891953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM 用于高速DRAM的3.6 Gb/s/pin同步双向(SBD) I/O接口
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332770
Jaekwan Kim, J. Choi, Sungcheol Shin, Chan-Kyong Kim, Hwa-Yong Kim, Woo-Seop Kim, Chan-Kyong Kim, Sooin Cho
{"title":"A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM","authors":"Jaekwan Kim, J. Choi, Sungcheol Shin, Chan-Kyong Kim, Hwa-Yong Kim, Woo-Seop Kim, Chan-Kyong Kim, Sooin Cho","doi":"10.1109/ISSCC.2004.1332770","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332770","url":null,"abstract":"A point-to-point I/O interface for high-speed DRAM is described. The interface utilizes simultaneous bidirectional signaling that enables transmitting/receiving data through a line at the same time. The test scheme is implemented in 0.10 /spl mu/m DRAM process. It achieves 3.6 Gb/s/pin in SBD mode and an I/O cell consumes 35 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121641628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Compact realization of active channel-select filters in wireless receivers 无线接收机中有源信道选择滤波器的紧凑实现
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332704
A. Ismail, A. Abidi
{"title":"Compact realization of active channel-select filters in wireless receivers","authors":"A. Ismail, A. Abidi","doi":"10.1109/ISSCC.2004.1332704","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332704","url":null,"abstract":"A coupled distributed oscillator is designed using low-loss MEMS coupled transmission lines to achieve phase noise improvement of 7dB, and an additional 2dB improvement is attributed to the MEMS transmission lines. The oscillators are fabricated in a 0.18/spl mu/m 6M CMOS process, operate with a 1V supply and consume 26mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114634825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1440/spl times/1080 pixels 30frames/s motion-JPEG2000 codec for HD movie transmission 用于高清电影传输的1440/spl倍/1080像素30帧/s运动- jpeg2000编解码器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332726
H. Yamauchi, K. Mochizuki, K. Taketa, T. Watanabe, T. Mori, Y. Matsuda, Y. Matsushita, A. Kobayashi, S. Okada
{"title":"A 1440/spl times/1080 pixels 30frames/s motion-JPEG2000 codec for HD movie transmission","authors":"H. Yamauchi, K. Mochizuki, K. Taketa, T. Watanabe, T. Mori, Y. Matsuda, Y. Matsushita, A. Kobayashi, S. Okada","doi":"10.1109/ISSCC.2004.1332726","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332726","url":null,"abstract":"The Motion-JPEG 2000 codec processor uses 0.18/spl mu/m technology. It integrates 18.6M transistors on a 92mm/spl times/9.2mm die and performs both decoding and compressing of 1440/spl times/1080 pixels with 30frames/s at 54MHz. A tile size obtained is 4096/spl times/2048 pixels and is sufficient for transmitting an HD movie. The IC runs up to 104MHz and dissipates 400mW at 1.8V and 54MHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124069254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers 实现了包含400个独立的低功耗、高线性度定时游标的量产ATE定制处理器和定时IC
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332737
B. Arkin
{"title":"Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers","authors":"B. Arkin","doi":"10.1109/ISSCC.2004.1332737","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332737","url":null,"abstract":"An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm/sup 2/ 62M transistor IC is implemented in foundry portable 0.18/spl mu/m CMOS technology.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121886060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
81MS/s JPEG2000 single-chip encoder with rate-distortion optimization 具有率失真优化的81MS/s JPEG2000单片机编码器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332727
Hung-Chi Fang, Chao-Tsung Huang, Yu-Wei Chang, Tu-Chih Wang, Po-Chih Tseng, Chung-Jr Lian, Liang-Gee Chen
{"title":"81MS/s JPEG2000 single-chip encoder with rate-distortion optimization","authors":"Hung-Chi Fang, Chao-Tsung Huang, Yu-Wei Chang, Tu-Chih Wang, Po-Chih Tseng, Chung-Jr Lian, Liang-Gee Chen","doi":"10.1109/ISSCC.2004.1332727","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332727","url":null,"abstract":"An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128/spl times/128, code block size of 64/spl times/64, and image size up to 32K/spl times/32K.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122845675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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