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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)最新文献

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A digital terrestrial television (ISDB-T) tuner for mobile applications 用于移动应用的数字地面电视(ISDB-T)调谐器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332702
S. Azuma, H. Kawamura, S. Kawama, S. Toyoyama, T. Hasegawa, K. Kagoshima, M. Koutani, H. Kijima, K. Sakuno, K. Iizuka
{"title":"A digital terrestrial television (ISDB-T) tuner for mobile applications","authors":"S. Azuma, H. Kawamura, S. Kawama, S. Toyoyama, T. Hasegawa, K. Kagoshima, M. Koutani, H. Kijima, K. Sakuno, K. Iizuka","doi":"10.1109/ISSCC.2004.1332702","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332702","url":null,"abstract":"A 160mW low-IF single-chip tuner for a mobile ISDB-T receiver is realized in SiGe BiCMOS. Its 25mW variable gain LNA shows 2.7dB NF and 62dB variable gain range. The 20mW switched-capacitor channel selection filter exhibits 80dB out-of-band rejection and 11nV//spl radic/Hz input referred noise.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134237051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Single-stage 378MHz 178k/spl Omega/ transimpedance amplifier with capacitive-coupled voltage dividers [optical fiber receiver applications] 带电容耦合分压器的单级378MHz 178k/spl欧米茄/跨阻放大器[光纤接收器应用]
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332798
C. Seidl, J. Knorr, H. Zimmermann
{"title":"Single-stage 378MHz 178k/spl Omega/ transimpedance amplifier with capacitive-coupled voltage dividers [optical fiber receiver applications]","authors":"C. Seidl, J. Knorr, H. Zimmermann","doi":"10.1109/ISSCC.2004.1332798","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332798","url":null,"abstract":"A transimpedance amplifier with an integrated photodiode in a 0.6 /spl mu/m BiCMOS technology is described. A transimpedance of 178 k/spl Omega/ and a bandwidth of 378 MHz for DVD applications are achieved with capacitively-coupled voltage dividers in the feedback path. An optical fiber receiver achieves a sensitivity of -30.4 dBm at 1 Gb/s.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132804311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Circuit design and noise considerations for future Blu-ray disc optical storage technology 未来蓝光光盘光存储技术的电路设计和噪声考虑
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332631
A. Stek, G. de Jong, Theo P. Jansen, J. Bergervoet, P. Woerlee
{"title":"Circuit design and noise considerations for future Blu-ray disc optical storage technology","authors":"A. Stek, G. de Jong, Theo P. Jansen, J. Bergervoet, P. Woerlee","doi":"10.1109/ISSCC.2004.1332631","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332631","url":null,"abstract":"The Blu-ray optical disc format for 25GB capacity is described. Low SNR is an issue for high-speed read-out and dual-layer discs. A non-linear equalizer circuit reduces low frequency media noise. Low-noise CMOS preamplifiers and the impact of CMOS scaling on SNR are presented.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133532500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 110dB ternary PWM current-mode audio DAC with monolithic 2Vrms driver 一个110dB三元PWM电流模式音频DAC与单片2Vrms驱动
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332749
Timothy T. Rueger, B. Duewer, Stephen T. Hodapp, T. Lei, J. Melanson, Brian David Trotter
{"title":"A 110dB ternary PWM current-mode audio DAC with monolithic 2Vrms driver","authors":"Timothy T. Rueger, B. Duewer, Stephen T. Hodapp, T. Lei, J. Melanson, Brian David Trotter","doi":"10.1109/ISSCC.2004.1332749","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332749","url":null,"abstract":"A /spl Delta//spl Sigma/ audio DAC uses a 4b quantizer, ternary PWM encoding, and semidigital current-mode FIRs for 110dB dynamic range over 20kHz. The IC achieves -99dB THD driving a single-ended 2V/sub rms/ signal into a 5k/spl Omega/ load. Die area is 5.98mm/sup 2/ in a 0.35/spl mu/m/3.3V process with a 3/spl mu/m/18V module.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133346899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 1 V 88 dB 20 kHz /spl Sigma//spl Delta/ modulator in 90 nm CMOS 1 V 88 dB 20 kHz /spl Sigma//spl Delta/ 90 nm CMOS调制器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332603
L. Yao, M. Steyaert, W. Sansen
{"title":"A 1 V 88 dB 20 kHz /spl Sigma//spl Delta/ modulator in 90 nm CMOS","authors":"L. Yao, M. Steyaert, W. Sansen","doi":"10.1109/ISSCC.2004.1332603","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332603","url":null,"abstract":"A third-order single-loop SC /spl Sigma//spl Delta/ modulator is realized in a standard 90 nm digital CMOS technology. The modulator achieves 88 dB dynamic range for a 20 kHz signal bandwidth with an OSR of 100. Power consumption is 140 /spl mu/W from a 1 V supply, and the chip core size is 0.18 mm/sup 2/.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133544911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Output buffer impedance control and noise reduction using a speed-locked loop 输出缓冲阻抗控制和噪声降低使用一个速度锁定环路
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332806
M. Bazes
{"title":"Output buffer impedance control and noise reduction using a speed-locked loop","authors":"M. Bazes","doi":"10.1109/ISSCC.2004.1332806","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332806","url":null,"abstract":"This paper presents a digital speed-locked loop (SLL) which controls the output buffer drive strength in an Ethernet controller chip. The SLL automatically determines the chip speed and adjusts the output buffer drive strength so that buffer impedance and switching noise remain within narrow limits over all process, voltage, and temperature conditions.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122248959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems 低抖动16:1 MUX和高灵敏度1:16 DEMUX，集成39.8至43GHz VCO，适用于OC-768通信系统
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332646
K. Watanabe, A. Koyama, T. Harada, T. Aida, A. Ito, T. Murata, H. Yoshioka, M. Sonehara, H. Yamashita, K. Ishikawa, M. Ito, N. Shiramizu, T. Nakamura, K. Ohhata, F. Arakawa, T. Kusunoki, H. Chiba, T. Kurihara, M. Kuraishi
{"title":"A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems","authors":"K. Watanabe, A. Koyama, T. Harada, T. Aida, A. Ito, T. Murata, H. Yoshioka, M. Sonehara, H. Yamashita, K. Ishikawa, M. Ito, N. Shiramizu, T. Nakamura, K. Ohhata, F. Arakawa, T. Kusunoki, H. Chiba, T. Kurihara, M. Kuraishi","doi":"10.1109/ISSCC.2004.1332646","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332646","url":null,"abstract":"A fully integrated 39.8 to 43Gb/s OC-768 16:1 MUX/DEMUX chipset is implemented in a 0.18/spl mu/m BiCMOS process. Full-rate operation is realized with an on-chip VCO, and the chipset dissipates 11.6W. The measured output jitter of the packaged MUX is 630fs, and the sensitivity of DEMUX is 31 mV/sub PP/ single-ended with a BER <10/sup -12/.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124865345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 12GHz silicon bipolar receiver for digital satellite applications 用于数字卫星应用的12GHz硅双极接收器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332701
G. Girlando, T. Copani, S. Smerzi, A. Castorina, G. Palmisano
{"title":"A 12GHz silicon bipolar receiver for digital satellite applications","authors":"G. Girlando, T. Copani, S. Smerzi, A. Castorina, G. Palmisano","doi":"10.1109/ISSCC.2004.1332701","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332701","url":null,"abstract":"A 12GHz monolithic silicon bipolar receiver for DVB-S applications is presented. The conversion gain is 33.6dB, SSB NF is 5.9dB, and out put P/sub -1dB/ is +5.5dBm. The VCO exhibits a phase noise of -102dBc/Hz at 100kHz offset from a 5.3GHz carrier. The VCO tuning range is 1.1 GHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125458161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers 一种用于3.1至10.6 GHz无线接收器的超宽带CMOS LNA
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332754
A. Bevilacqua, A. Niknejad
{"title":"An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers","authors":"A. Bevilacqua, A. Niknejad","doi":"10.1109/ISSCC.2004.1332754","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332754","url":null,"abstract":"A UWB 3.1 to 10.6 GHz LNA employing an input three-section band-pass Chebyshev filter is reported. Fabricated in a 0.18 /spl mu/m CMOS process, -10 dB over the band, a NF of 4 dB, and an IIP3 of -6.7 dBm while consuming the IC achieves a power gain of 9.3 dB with an input match of 9 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125667850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 278
A 17.1 to 17.3 GHz image-reject down-converter with phase-tunable LO using 3/spl times/ subharmonic injection locking 一个17.1到17.3 GHz的图像抑制下变频器，具有相位可调的LO，使用3/spl次/次谐波注入锁定
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332757
S.Y. Yue, D. Ma, J. Long, B. Jagannathan, D. Harame
{"title":"A 17.1 to 17.3 GHz image-reject down-converter with phase-tunable LO using 3/spl times/ subharmonic injection locking","authors":"S.Y. Yue, D. Ma, J. Long, B. Jagannathan, D. Harame","doi":"10.1109/ISSCC.2004.1332757","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332757","url":null,"abstract":"A 17 GHz RF receiver consisting of an LNA and doubly-balanced mixers coupled by a monolithic 3.7:1 step-down transformer realizes over 70 dB of image-rejection in a 100 GHz-f/sub T/ SiGe BiCMOS technology. Quadrature LO signals are generated with electronically tunable phase from a subharmonically injection-locked oscillator. The measured IIP3 is -5.1 dBm with 17.3 dB conversion gain and 6.5 dB NF (SSB, 50 /spl Omega/) at 17.2 GHz. The 1.9/spl times/1.0 mm/sup 2/ IC consumes 62.5 mW from a 2.2 V supply.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128839050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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