输出缓冲阻抗控制和噪声降低使用一个速度锁定环路

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332806

M. Bazes

{"title":"输出缓冲阻抗控制和噪声降低使用一个速度锁定环路","authors":"M. Bazes","doi":"10.1109/ISSCC.2004.1332806","DOIUrl":null,"url":null,"abstract":"This paper presents a digital speed-locked loop (SLL) which controls the output buffer drive strength in an Ethernet controller chip. The SLL automatically determines the chip speed and adjusts the output buffer drive strength so that buffer impedance and switching noise remain within narrow limits over all process, voltage, and temperature conditions.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Output buffer impedance control and noise reduction using a speed-locked loop\",\"authors\":\"M. Bazes\",\"doi\":\"10.1109/ISSCC.2004.1332806\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital speed-locked loop (SLL) which controls the output buffer drive strength in an Ethernet controller chip. The SLL automatically determines the chip speed and adjusts the output buffer drive strength so that buffer impedance and switching noise remain within narrow limits over all process, voltage, and temperature conditions.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332806\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332806","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 16

摘要

本文提出了一种数字式锁速环路(SLL)，用于控制以太网控制器芯片的输出缓冲区驱动强度。SLL自动确定芯片速度并调整输出缓冲器驱动强度，使缓冲器阻抗和开关噪声在所有工艺、电压和温度条件下保持在狭窄的限制范围内。

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Output buffer impedance control and noise reduction using a speed-locked loop

This paper presents a digital speed-locked loop (SLL) which controls the output buffer drive strength in an Ethernet controller chip. The SLL automatically determines the chip speed and adjusts the output buffer drive strength so that buffer impedance and switching noise remain within narrow limits over all process, voltage, and temperature conditions.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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