P. Quinlan, P. Crowley, M. Chanca, S. Hudson, B. Hunt, K. Mulvaney, G. Retz, C. O'Sullivan, P. Walsh
{"title":"A multi-mode 0.3-128kb/s transceiver for the 433/868/915MHz ISM bands in 0.25/spl mu/m CMOS","authors":"P. Quinlan, P. Crowley, M. Chanca, S. Hudson, B. Hunt, K. Mulvaney, G. Retz, C. O'Sullivan, P. Walsh","doi":"10.1109/ISSCC.2004.1332700","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332700","url":null,"abstract":"A fully integrated ISM-band transceiver in 0.25/spl mu/m CMOS for low data-rate wireless networks consumes 17mA from a 3V supply in FIX mode. At +10dBm output power, the part consumes 24mA. G/FSK and OOK/ASK modulation formats are supported at data rates from 0.3-128kb/s in the 433/868/915MHz ISM bands.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128949760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Carlstrom, G. Nordmark, J. Roos, T. Boden, L. Svensson, P. Westlund
{"title":"A 40 Gb/s network processor with PISC/spl trade/ dataflow architecture","authors":"J. Carlstrom, G. Nordmark, J. Roos, T. Boden, L. Svensson, P. Westlund","doi":"10.1109/ISSCC.2004.1332593","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332593","url":null,"abstract":"This 40 Gb/s network processor has a dataflow architecture with 200 PISC/spl trade/ processors, organized in a linear array, also containing 11 I/O processors which interconnect to on-chip or off-chip engines. Implemented in a 0.13 /spl mu/m CMOS process, the chip has 114M transistors and It typically dissipates 9.5 W at 200 MHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128746432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu-Wei Lin, Seungbae Lee, Sheng-Shian Li, Yuan Xie, Z. Ren, C. Nguyen
{"title":"60-MHz wine-glass micromechanical-disk reference oscillator","authors":"Yu-Wei Lin, Seungbae Lee, Sheng-Shian Li, Yuan Xie, Z. Ren, C. Nguyen","doi":"10.1109/ISSCC.2004.1332724","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332724","url":null,"abstract":"A reference oscillator utilizing a 60MHz, MEMS-based, wine glass disk vibrating micromechanical resonator with a Q of 48,000 and sufficient power handling capability to achieve a far-from-carrier phase noise of -130dBc/Hz is demonstrated. When divided down to 10MHz, this corresponds to an effective level of -145dBc/Hz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"496 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116200892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar, V. De
{"title":"Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique","authors":"S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar, V. De","doi":"10.1109/ISSCC.2004.1332641","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332641","url":null,"abstract":"A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more than 2.6x frequency improvement at 0.5V Vcc and the ability to reduce Vcc by 0.2V for the same frequency compared to no body bias in 180 to 90nm CMOS technologies.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121716643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection","authors":"O. Stroeble, V. Dias, C. Schwoerer","doi":"10.1109/ISSCC.2004.1332794","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332794","url":null,"abstract":"A 10 b 80 MHz pipeline ADC consumes 22 mA at 1.5 V and occupies a die area of 0.3 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology. The ADC is based on a conventional 1.5 b pipeline architecture combined with dynamic-range-doubling and dynamic-reference-selection algorithms.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125822809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Fujita, K. Uchida, S. Yasuda, R. Ohba, H. Nozaki, T. Tanamoto
{"title":"Si nanodevices for random number generating circuits for cryptographic security","authors":"S. Fujita, K. Uchida, S. Yasuda, R. Ohba, H. Nozaki, T. Tanamoto","doi":"10.1109/ISSCC.2004.1332710","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332710","url":null,"abstract":"Small random-number-generating circuits for cryptographic security using Si nano-devices are described. The basis of these circuits is that nano-devices hold random electrical properties naturally that were previously regarded as a negative feature. Results of statistical tests indicate that these circuits generate extremely high-quality random numbers with relatively few transistors.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125999719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Nagatsuma, A. Hirata, M. Harada, H. Ishii, K. Machida, T. Minotani, H. Ito, T. Kosugi, T. Shibata
{"title":"Millimeter-wave photonic integrated circuit technologies for high-speed wireless communications applications","authors":"T. Nagatsuma, A. Hirata, M. Harada, H. Ishii, K. Machida, T. Minotani, H. Ito, T. Kosugi, T. Shibata","doi":"10.1109/ISSCC.2004.1332787","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332787","url":null,"abstract":"This paper describes an IC technology for high-speed wireless-link systems, using photonic techniques, which provides 10 Gb/s at 120 GHz. Optical signals are converted to electrical signals and radiated into freespace using Si-based circuitry. Both the preamp and PA utilize 0.1 /spl mu/m gate InAlAs/InGaAs HEMTs with gains of 6-10 dB and 8.5 dB, respectively.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127146556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Morishita, I. Hayashi, H. Matsuoka, K. Takahashi, K. Shigeta, T. Gyohten, M. Niiro, M. Okamoto, A. Hachisuka, A. Amo, H. Shinkawata, T. Kasaoka, K. Dosaka, K. Arimoto
{"title":"A 312MHz 16Mb random-cycle embedded DRAM macro with 73/spl mu/W power-down mode for mobile applications","authors":"F. Morishita, I. Hayashi, H. Matsuoka, K. Takahashi, K. Shigeta, T. Gyohten, M. Niiro, M. Okamoto, A. Hachisuka, A. Amo, H. Shinkawata, T. Kasaoka, K. Dosaka, K. Arimoto","doi":"10.1109/ISSCC.2004.1332664","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332664","url":null,"abstract":"An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is 73/spl mu/W, which is 5% compared to a conventional one.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128077354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Hernes, A. Briskemyr, T. N. Andersen, F. Telste, T. E. Bonnerud, O. Moldsvor
{"title":"A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13/spl mu/m digital CMOS","authors":"B. Hernes, A. Briskemyr, T. N. Andersen, F. Telste, T. E. Bonnerud, O. Moldsvor","doi":"10.1109/ISSCC.2004.1332691","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332691","url":null,"abstract":"A 10b pipeline ADC fabricated in a 0.13/spl mu/m pure digital CMOS process is presented. The supply voltage is 1.2V and the conversion rate is 120MS/s. The ADC maintains its performance down to 0.9V supply voltage and up to 220MS/s at a signal swing near full scale. Power consumption at 220MS/s is 135mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"887 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127346570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ezaki, K. Kondo, H. Ozaki, N. Sasaki, H. Yonernura, M. Kitano, S. Tanaka, T. Hirayarna
{"title":"A 160Gb/s interface design configuration for multichip LSI","authors":"T. Ezaki, K. Kondo, H. Ozaki, N. Sasaki, H. Yonernura, M. Kitano, S. Tanaka, T. Hirayarna","doi":"10.1109/ISSCC.2004.1332633","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332633","url":null,"abstract":"The Multichip LSI (MCL) comprised of both an embedded 123MHz CPU and a 64Mb memory in one package is introduced. 1300 signal lines are directly connected by microbumps between the two chips and achieve 160Gb/s signal interface performance. Both the CPU and memory are fabricated in a 0.15/spl mu/m CMOS technology.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132058554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}