80mhz 10b流水线ADC，具有动态范围倍增和动态参考选择功能

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332794

O. Stroeble, V. Dias, C. Schwoerer

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引用次数: 31

摘要

在0.13 /spl mu/m CMOS技术中，10b 80 MHz流水线ADC在1.5 V下消耗22 mA，占据0.3 mm/sup / /的芯片面积。ADC基于传统的1.5 b管道架构，结合了动态范围加倍和动态参考选择算法。

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An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection

A 10 b 80 MHz pipeline ADC consumes 22 mA at 1.5 V and occupies a die area of 0.3 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology. The ADC is based on a conventional 1.5 b pipeline architecture combined with dynamic-range-doubling and dynamic-reference-selection algorithms.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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