一个40gb /s的网络处理器，带有PISC/spl交易/数据流架构

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332593

J. Carlstrom, G. Nordmark, J. Roos, T. Boden, L. Svensson, P. Westlund

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引用次数: 4

摘要

这个40 Gb/s的网络处理器有一个数据流架构，有200个PISC/spl的贸易/处理器，以线性阵列组织，还包含11个I/O处理器，它们与片上或片外引擎互连。该芯片采用0.13 /spl mu/m CMOS工艺，拥有114M晶体管，在200mhz时功耗为9.5 W。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 40 Gb/s network processor with PISC/spl trade/ dataflow architecture

This 40 Gb/s network processor has a dataflow architecture with 200 PISC/spl trade/ processors, organized in a linear array, also containing 11 I/O processors which interconnect to on-chip or off-chip engines. Implemented in a 0.13 /spl mu/m CMOS process, the chip has 114M transistors and It typically dissipates 9.5 W at 200 MHz.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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