A 40 Gb/s network processor with PISC/spl trade/ dataflow architecture

Abstract

This 40 Gb/s network processor has a dataflow architecture with 200 PISC/spl trade/ processors, organized in a linear array, also containing 11 I/O processors which interconnect to on-chip or off-chip engines. Implemented in a 0.13 /spl mu/m CMOS process, the chip has 114M transistors and It typically dissipates 9.5 W at 200 MHz.