A 160Gb/s interface design configuration for multichip LSI

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332633

T. Ezaki, K. Kondo, H. Ozaki, N. Sasaki, H. Yonernura, M. Kitano, S. Tanaka, T. Hirayarna

引用次数: 76

Abstract

The Multichip LSI (MCL) comprised of both an embedded 123MHz CPU and a 64Mb memory in one package is introduced. 1300 signal lines are directly connected by microbumps between the two chips and achieve 160Gb/s signal interface performance. Both the CPU and memory are fabricated in a 0.15/spl mu/m CMOS technology.

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多芯片LSI 160Gb/s接口设计配置

介绍了将123MHz的嵌入式CPU和64Mb的内存集成在一个封装中的多芯片LSI (MCL)。两个芯片之间通过微凸起直接连接1300条信号线，实现160Gb/s的信号接口性能。CPU和存储器均采用0.15/spl mu/m CMOS技术制造。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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