采用交换体偏置技术的180nm至90nm超低电压电路和处理器

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332641

S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar, V. De

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引用次数: 94

摘要

研究了PMOS体接地、NMOS体接Vcc的低压交换体偏置技术。现有的测量结果表明，与180至90nm CMOS技术中无体偏相比，在0.5V Vcc下频率提高了2.6倍以上，并且在相同频率下能够将Vcc降低0.2V。

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Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

A low-voltage swapped-body biasing technique where PMOS bodies are connected to ground and NMOS bodies to Vcc is evaluated. Available measurements show more than 2.6x frequency improvement at 0.5V Vcc and the ability to reduce Vcc by 0.2V for the same frequency compared to no body bias in 180 to 90nm CMOS technologies.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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