An SoC with two multimedia DSPs and a RISC core for video compression applications

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332728

H. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, Mladen Berekovic, P. Pirsch

引用次数: 26

Abstract

An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm/sup 2/ chip is implemented in a 0.18/spl mu/m 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.

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具有两个多媒体dsp和用于视频压缩应用的RISC核心的SoC

SoC由一个带有2D矩阵存储器的16路SIMD DSP内核、一个具有子字并行性的64b VLIW DSP内核和一个32b RISC内核组成。81mm/sup 2/芯片采用0.18/spl mu/m 6M标准单元技术，运行频率为145MHz。该设备可以进行D1分辨率的MPEG-4高级简单配置文件解码、MPEG-4编码和实时目标分割。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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