Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers

Abstract

An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm/sup 2/ 62M transistor IC is implemented in foundry portable 0.18/spl mu/m CMOS technology.